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ADC0808S125/DB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 24 February 2009 7 of 23
NXP Semiconductors
ADC0808S125/250
Single 8-bit ADC, up to 125 MHz or 250 MHz
7.3 Timing output
7.4 Timing complete conversion signal
The ADC0808S generates an adjustable clock output signal on pin CCS called Complete
Conversion Signal, which can be used to control the acquisition of converted output data
to the digital circuit connected to the ADC0808S output data bus.
Two logic input pins DEL0 and DEL1 control the delay of the edge of the CCS signal to
achieve an optimal position in the stable, usable zone of the data as shown in Figure 6.
Pin CCSSEL selects the CCS frequency; see Table 8.
Fig 5. Output timing diagram (CCS not selected)
IN, INN
CLK+, CLK−
n
D0 to D7
50 %
data
n − 2n − 1
data data data
n + 1n
t
d(o)
t
d(s)
t
h(o)
001aab892
sample
n
sample
n + 1
sample
n + 2
sample
n + 3
sample
n + 4
Table 7. Complete conversion signal selection
Pin DEL0 Pin DEL1 Pin CCS
LOW LOW high-impedance
HIGH LOW active; see
Table 13
LOW HIGH
HIGH HIGH
Table 8. Complete conversion signal frequency selection
Pin CCSSEL CCS frequency (f
CCS
)
HIGH or not connected f
clk
LOW f
clk
/ 2
ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 24 February 2009 8 of 23
NXP Semiconductors
ADC0808S125/250
Single 8-bit ADC, up to 125 MHz or 250 MHz
7.5 Full-scale input selection
The ADC0808S has an internal reference circuit which can be overruled by an external
reference voltage. This can be done with the full-scale reference voltage (V
ref(fs)
)
according to Table 9.
The ADC provides the required common-mode voltage on pin CMADC. In case of internal
regulation, the regulator output voltage on pin CMADC is 0.95 V.
The internal reference circuit is enabled by connecting pin FSIN to ground. The
common-mode output voltage V
O(cm)
on pin CMADC will then be 0.95 V, and the
maximum peak-to-peak input voltage V
i(p-p)(max)
will be 2.0 V; see Figure 7 and Figure 8.
The ADC full-scale input selection principle is shown in Figure 9.
Fig 6. Complete conversion signal timing diagram using CCS
001aab893
CCS (f
clk
)
CCS (f
clk
/ 2)
D0 to D7
50 %
50 %
data
n − 2n − 1
data data data
n + 1n
t
d(CCS)
Table 9. Full-scale input selection
Full-scale reference voltage
V
ref(fs)
Common-mode output
voltage V
O(cm)
Maximum peak-to-peak input
voltage V
i(p-p)(max)
1.15 V 0.8 V 1.825 V
1.20 V 0.86 V 1.91 V
1.25 V 0.94 V 1.99 V
1.30 V 1.01 V 2.08 V
1.35 V 1.09 V 2.16 V
ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 24 February 2009 9 of 23
NXP Semiconductors
ADC0808S125/250
Single 8-bit ADC, up to 125 MHz or 250 MHz
Fig 7. ADC common-mode output voltage V
O(cm)
as a function of V
FSIN
Fig 8. ADC maximum peak-to-peak input voltage V
i(p-p)(max)
as a function of V
FSIN
V
FSIN
(V)
0 1.41.31.21.1
001aai270
0.9
0.8
1.0
1.1
V
O(cm)
(V)
0.7
V
FSIN
(V)
1.0 1.41.31.21.1
001aai269
2.0
1.9
2.1
2.2
V
i(p-p)(max)
(V)
1.8
a. External reference voltage applied b. Internal reference circuit enabled
Fig 9. ADC full-scale input selection
IN analog
input
1.15 V to 1.35 V
0.8 V to 1.1 V
INN
FSIN/REFSEL
CMADC
001aai273
IN analog
input
0.95 V
INN
FSIN/REFSEL
CMADC
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ADC0808S125/DB

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NXP Semiconductors
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