NCN6000
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10
DIGITAL PARAMETERS SECTION @ 2.70 VvVbatv6.0 V, NORMAL OPERATING MODE (−25°C to +85°C ambient
temperature, unless otherwise noted.) Note: Digital inputs undershoot < −0.30 V to ground, Digital inputs overshoot <0.30 V to Vbat
Rating Symbol Pin Min Typ Max Unit
Input Asynchronous Clock Duty Cycle = 50%
@ Vbat = 3.0V over the temperature range
F
CLKIN
10
40 MHz
Clock Rise Time
Clock Fall Time
F
tr
F
tf
10
5.0
5.0
ns
I/O Data Transfer Switching Time,
Both Directions (I/O and CRD_IO),
@ Cout = 30 pF
I/O Rise Time* (Note 7)
I/O Fall Time
T
RIO
T
FIO
8, 14
0.8
0.8
s
Input/Output Data Transfer Time, Both Directions
@ 50% CRD_VCC, L to H and H to L
T
TIO
8, 14 150 ns
Minimum PWR_ON Low Level Logic State Time
to Power Down the DC−DC Converter
T
WON
4 2.0
s
CRD_VCC Power Up/Down Sequence Interval T
DSEQ
0.5 2.0
s
STATUS Pull Up Resistance R
STA
5 20 50 80
k
Chip Select CS Pull Up Resistance R
CSPU
6 20 50 80
k
Interrupt INT Pull Up Resistance R
INTPU
9 20 50 80
k
Positive Going Input High Voltage Threshold (A0,
A1, PGM, PWR_ON, CS, RESET, CRD_DET)
V
IH
1, 2,
3, 4,
6, 7,
11
0.70 * Vbat Vbat V
Negative Going Input High Voltage Threshold
(A0, A1, PGM, PWR_ON, CS, RESET,
CRD_DET)
V
IL
1, 2,
3, 4,
6, 7,
11
0 0.30 * Vbat V
Output High Voltage
STATUS, INT @ I
OH
= −10 A
V
OH
5, 9 Vbat − 1.0 V V
Output High Voltage
STATUS, INT @ I
OH
= 200 A
V
OL
5, 9 0.40 V
7. Since a 20 k pull up resistor is provided by the NCN6000, the external MPU can use an Open Drain connection.
DIGITAL PARAMETERS SECTION @ 2.70 VvVbatv6.0 V, CHIP PROGRAMMING MODE (−25°C to +85°C ambient
temperature, unless otherwise noted.)
Rating Symbol Pin Min Typ Max Unit
A0, A1, PGM, PWR_ON, RESET and I/O
Data Set Up Time
T
SMOD
1, 2,
3, 4,
7, 8
2.0
s
A0, A1, PGM, PWR_ON, RESET and I/O
Data Set Up Time
T
HMOD
1, 2,
3, 4,
7, 8
2.0
s
Chip Select CS Low State Pulse Width T
WCS
6 2.0
s
NCN6000
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11
SMART CARD SECTION (−25°C to +85°C ambient temperature, unless otherwise noted.)
Rating
Symbol Pin Min Typ Max Unit
CRD_RST @ CRD_VCC = +5.0 V
Output RESET V
OH
@ Icrd_rst = −20 A
Output RESET V
OL
@ Icrd_rst = 200 A
Output RESET
Rise Time @ Cout = 30 pF
Output RESET
Fall Time @ Cout = 30 pF
CRD_RST @ Vcc = +3.0 V
Output RESET V
OH
@ Icrd_rst = −20 A
Output RESET V
OL
@ Icrd_rst = 200 A
Output RESET Rise Time @ Cout = 30 pF
Output RESET Fall Time @ Cout = 30 pF
V
OH
V
OL
t
R
t
F
V
OH
V
OL
t
R
t
F
12
CRD_VCC − 0.9
0
CRD_VCC − 0.9
0
CRD_VCC
0.4
100
100
CRD_VCC
0.4
100
100
V
V
ns
ns
V
V
ns
ns
CRD_CLK @ CRD_VCC = +3.0 V or +5.0 V
CRD_VCC = +5.0 V
Output Frequency (See Note 8)
Output Duty Cycle @ DC Fin = 50% "1%
Output CRD_CLK Rise Time @ Cout = 30 pF
Output CRD_CLK Fall Time @ Cout = 30 pF
Output V
OH
@ Icrd_clk = −20 A
Output V
OL
@ Icrd_clk = 100 A
CRD_VCC = +3.0 V
Output Frequency (See Note 8)
Output Duty Cycle @ DC Fin = 50% "1%
Output CRD_CLK Rise Time @ Cout = 30 pF
Output CRD_CLK Fall Time @ Cout = 30 pF
Output V
OH
@ Icrd_clk = −20 A @ Cout = 30 pF
Output V
OL
@ Icrd_clk = 100 A @ Cout = 30 pF
F
CRDCLK
F
CRDDC
t
R
t
F
V
OH
V
OL
F
CRDCLK
F
CRDDC
t
R
t
F
V
OH
V
OL
13
45
3.15
0
40
1.85
0
5.0
55
18
18
CRD_VCC
+0.5
5.0
60
18
18
CRD_VCC
0.7
MHz
%
ns
ns
V
V
MHz
%
ns
ns
V
V
CRD_I/O @ CRD_VCC = +5.0 V
CRD_I/O Data Transfer Frequency
CRD_I/O Rise Time @ Cout = 30 pF
CRD_I/O Fall Time @ Cout = 30 pF
Output V
OH
@ Icrd_i/o = −20 A
Output V
OL
@ Icrd_i/o = 500 A, V
IL
= 0 V
CRD_I/O @ CRD_VCC = +3.0 V
CRD_I/O Data Transfer Frequency
CRD_I/O Rise Time @ Cout = 30 pF
CRD_I/O Fall Time @ Cout = 30 pF
Output V
OH
@ Icrd_i/o = −20 A
Output V
OL
@ Icrd_i/o = 500 A, V
IL
= 0 V
F
IO
T
RIO
T
FIO
V
OH
V
OL
F
IO
T
RIO
T
FIO
V
OH
V
OL
14
CRD_VCC − 0.9
0
CRD_VCC − 0.9
0
315
315
0.8
0.8
CRD_VCC
0.4
0.8
0.8
CRD_VCC
0.4
kHz
s
s
V
V
kHz
s
s
V
V
CRD_IO Pull Up Resistor @ PWR_ON = H R
CRDPU
14 14 20 26
k
Card Detection Debouncing Delay:
Card Insertion
Card Extraction
T
CRDIN
T
CRDOFF
11
50
50
150
150
s
s
Card Insertion or Extraction Positive Going Input
High Voltage
V
IHDET
11 0.70 * Vbat Vbat V
Card Insertion or Extraction Negative Going Input
Low Voltage
V
ILDET
11 0 0.30 * Vbat V
Card Detection Bias Pull Up Current @
Vbat = 5.0 V
I
DET
11 10
A
Output Peak Max Current Under Card Static
Operation Mode @ Vcc = 3.0 V or Vcc = 5.0 V
Icrd_iorst 12, 14 15 mA
Output Peak Max Current Under Card Static
Operation Mode @ Vcc = 3.0 V or Vcc = 5.0 V
Icrd_clk 13 70 mA
8. The CRD_CLK clock can operate up to 20 MHz, but the rise and fall time are not guaranteed to be fully within the ISO7816 specification over
the temperature range. Typically, tr and tf are 12 ns @ CRD_CLK = 10 MHz.
NCN6000
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12
Programming and Status Functions
The NCN6000 features a programming interface and a status interface. Figure 4 illustrates the programming mode.
Table 1. Programming and Status Functions Pinout Logic
Pins Name
CRD_VCC
Prg. 3.0 V/5.0 V
CLOCK_IN
Divide Ratio
CRD_DET
CLOCK STOP
AND START
Poll Card
Status
DC−DC
Status
Vbat
Status
CRD_VCC
Status
5 STATUS Not Affected Not Affected Not Affected Not Affected READ READ READ READ
6 CS Latch On
Rising Edge
Latch On
Rising Edge
Latch On
Rising Edge
Latch On
Rising Edge
0 0 0 0
3 PGM 0 0 0 0 1 1 1 1
1 A0 0/1 0/1 0/1 0/1 0 1 0 1
2 A1 0/1 0/1 1 0 0 0 1 1
7 RESET 0 0 1 1 Z Z Z Z
8 I/O (in) 0/1 0/1 0/1 0/1 Z Z Z Z
The PGM signal, pin 3, controls the mode of operation (chip programming or smart card transaction) and must be set up
accordingly prior to pull Chip Select (pin 6) Low.
Table 2. Status Pin Logic Output
Name CS PGM A1 A0 Status Logic Level
None H X X X No Chip Access
None L L X X Programming Mode, No Read Available
CARD PRESENT L H L L Low: No Card Inserted
High: Card inserted
DC−DC L H L H Low: DC−DC Over Range
High: DC−DC Operates Normally
Vbat L H H L Low: Vbat Within Range
High: Vbat Below Minimum range
CRD_VCC Overload L H H H Low: CRD_VCC Voltage Below Minimum Range
High: CRD_VCC in Range

NCN6000DTBG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC SMART CARD COMPACT 20-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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