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ADCMP607BCPZ-R7

P1-P3P4-P6P7-P9P10-P12P13-P14
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply CML Comparators
Data Sheet
ADCMP606/ADCMP607
Rev. C Document Feedback
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FEATURES
Fully specified rail to rail at V
CCI
= 2.5 V to 5.5 V
Input common-mode voltage from −0.2 V to V
CCI
+ 0.2 V
CML-compatible output stage
1.25 ns propagation delay
50 mW at 2.5 V power supply
Shutdown pin
Single-pin control for programmable hysteresis and latch
(ADCMP607 only)
Power supply rejection > 60 dB
−40°C to +125°C operation
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)
GENERAL DESCRIPTION
The ADCMP606 and ADCMP607 are very fast comparators
fabricated on XFCB2, an Analog Devices, Inc., proprietary
process. These comparators are exceptionally versatile and easy
to use. Features include an input range from V
EE
− 0.5 V to
V
CCI
+ 0.2 V, low noise, CML-compatible output drivers, and
TTL-/CMOS-compatible latch inputs with adjustable hysteresis
and/or shutdown inputs.
The devices offer 1.25 ns propagation delay with 2.5 ps rms
random jitter (RJ). Overdrive and slew rate dispersion are
typically less than 50 ps.
A flexible power supply scheme allows the devices to operate
with a single +2.5 V positive supply and a −0.5 V to +2.7 V
input signal range up to a +5.5 V positive supply with a −0.5 V
to +5.7 V input signal range. The ADCMP607 features split
input/output supplies with no sequencing restrictions to
support a wide input signal range with independent output
swing control and power savings.
The CML-compatible output stage is fully back-matched for
superior performance. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded. On
the ADCMP607, latch and programmable hysteresis features are
also provided with a unique single-pin control option.
The ADCMP606 is available in a 6-lead SC70 package and the
ADCMP607 is available in a 12-lead LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
V
P
NONINVERTING
INPUT
V
N
INVERTING
INPUT
S
DN
INPUT (ADCMP607 ONLY)
V
CCI
V
CCO
(ADCMP607 ONLY)
Q OUTPUT
Q OUTPUT
LE/HYS INPUT (ADCMP607 ONLY)
ADCMP606/
ADCMP607
CML
05917-001
F
igure 1.
ADCMP606/ADCMP607 Data Sheet
Rev. C | Page 2 of 14
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Timing Information ..................................................................... 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Applications Information .............................................................. 10
Power/Ground Layout and Bypassing ..................................... 10
CML-Compatible Output Stage ............................................... 10
Using/Disabling the Latch Feature ........................................... 10
Optimizing Performance ........................................................... 10
Comparator Propagation Delay Dispersion ............................... 11
Comparator Hysteresis .............................................................. 11
Crossover Bias Points ................................................................. 12
Minimum Input Slew Rate Requirement ................................ 12
Typical Application Circuits ......................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
4/16—Rev. B to Rev. C
Changes to Figure 4 and Table 6 ..................................................... 7
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
11/14—Rev. A to Rev. B
Changes to Figure 4 and Table 6 ..................................................... 7
Changes to Figure 12 and Figure 13 ............................................... 9
Changes to Comparator Hysteresis Section ................................ 11
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
8/07—Rev. 0 to Rev. A
Changes to Specifications Section .................................................. 3
Changes to Table 3 ............................................................................ 6
Changes to Ordering Guide .......................................................... 14
10/06—Revision 0: Initial Version
Data Sheet ADCMP606/ADCMP607
Rev. C | Page 3 of 14
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
CCI
= V
CCO
= 2.5 V, T
A
= −40°C to +125°C, typical at T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DC INPUT CHARACTERISTICS
Voltage Range V
P
, V
N
V
CCI
= 2.5 V to 5.5 V −0.5 V
CCI
+ 0.2 V
Common-Mode Range V
CCI
= 2.5 V to 5.5 V −0.2 V
CCI
+ 0.2 V
Differential Voltage V
CCI
= 2.5 V to 5.5 V V
CCI
V
Offset Voltage V
OS
−5.0 +5.0 mV
Bias Current I
P
, I
N
−5.0 ±2 +5.0 µA
Offset Current −2.0 2.0 µA
Capacitance C
P
, C
N
1 pF
Resistance, Differential Mode −0.1 V to V
CCI
200 700 kΩ
Resistance, Common Mode −0.5 V to V
CCI
+ 0.5 V 100 350 kΩ
Active Gain A
V
85 dB
Common-Mode Rejection Ratio CMRR V
CCI
= 2.5 V, V
CCO
= 2.5 V,
V
CM
= −0.2 V to +2.7 V
50 dB
V
CCI
= 2..5 V, V
CCO
= 5.5 V
50
dB
Hysteresis
R
HYS
= ∞
<0.1
mV
LATCH ENABLE PIN CHARACTERISTICS
(ADCMP607 Only)
V
IH
Hysteresis is shut off
2.0
CCO
V
V
IL
Latch mode guaranteed −0.2 +0.4 +0.8 V
I
IH
V
IH
= V
CCO
−6 +6 µA
I
IL
V
IL
= 0.4 V −0.1 +0.1 mA
HYSTERESIS MODE AND TIMING
Hysteresis Mode Bias Voltage Current sink 0 µA 1.145 1.25 1.35 V
Minimum Resistor Value Hysteresis = 120 mV 55 75 110 kΩ
Latch Setup Time t
S
V
OD
= 50 mV −1.5 ns
Latch Hold Time t
H
V
OD
= 50 mV 2.3 ns
Latch-to-Output Delay t
PLOH
, t
PLOL
V
OD
= 50 mV 30 ns
Latch Minimum Pulse Width t
PL
V
OD
= 50 mV 25 ns
SHUTDOWN PIN CHARACTERISTICS
(ADCMP607 Only)
V
IH
Comparator is operating 2.0 V
CCO
V
V
IL
Shutdown guaranteed −0.2 +0.4 +0.6 V
I
IH
V
IH
= V
CCO
−6 +6 µA
I
IL
V
IL
= 0 V −0.1 mA
Sleep Time t
SD
10% output swing <1 ns
Wake-Up Time t
H
V
OD
= 100 mV, output valid 35 ns
DC OUTPUT CHARACTERISTICS
V
CCO
= 2.5 V to 5.5 V
Output Voltage High Level V
OH
50 Ω terminate to V
CCO
V
CCO
− 0.1 V
CCO
− 0.05 V
CCO
V
Output Voltage Low Level V
OL
50 Ω terminate to V
CCO
V
CCO
− 0.6 V
CCO
− 0.45 V
CCO
− 0.3 V
Output Voltage Differential 50 Ω terminate to V
CCO
300 400 500 mV
P1-P3P4-P6P7-P9P10-P12P13-P14

ADCMP607BCPZ-R7

Mfr. #:
Buy ADCMP607BCPZ-R7
Manufacturer:
Analog Devices Inc.
Description:
Analog Comparators RR Fast 2.5-5.5V SGL-Supply CML
Lifecycle:
New from this manufacturer.
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