NB3N51054
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4
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two−signal I
2
C serial interface is provided. All the clock
outputs can be individually enabled or disabled in a glitch free manner though this serial data interface. In addition, spread
spectrum can be enabled for −0.35% or −0.5% down spread or no spread option can be selected though this interface. The
registers associated with the serial interface initialize to their default settings upon power−up.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write and block read operations from the controller. For
block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first)
with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system
controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described
in Table 2 below.
Table 2. COMMAND CODE DEFINITION
Bit Description
7 0 = Block read or Block write operation, 1= Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For Block read or Block write operations, these bits should be ‘0000000’.
The block write and block read protocol is outlined in Table 3, while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 3. BLOCK READ AND BLOCK WRITE PROTOCOL
Block Write Protocol Block Read Protocol
Bit Description Bit Description
1 Start 1 Start
2:8 Slave address – 7 bits 2:8 Slave address – 7 bits
9 Write = 0 9 Write = 0
10 Acknowledge from slave 10 Acknowledge from slave
11:18 Command code – 8 bit
‘00000000’ stands for block operation
11:18 Command code – 8 bit
‘00000000’ stands for block operation
19 Acknowledge from slave 19 Acknowledge from slave
20:27 Byte count – 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address – 7 bits
29:36 Data byte 0 – 8 bits 28 Read = 1
37 Acknowledge from slave 29 Acknowledge from slave
38:45 Data byte 1 – 8 bits 30:37 Byte count from slave – 8 bits
46 Acknowledge from slave 38 Acknowledge from master
… …………
39:46 Data byte from slave – 8 bits
…
Data byte (N−1) – 8 bits 47 Acknowledge from master
…
Acknowledge from slave 48:55 Data byte from slave – 8 bits
…
Data byte N – 8 bits 56 Acknowledge from master
Acknowledge from slave
…
Data byte N from slave – 8 bits
…
Stop
…
Not Acknowledge from master
…
Stop
