BU2099FV-E2 Datasheet BU2152FS-E2, BU2092FV-E2, BU2099FV-E2 | P13-P15

BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS

Technical Note

13/24

www.rohm.com

2009.06 - Rev.A

【BU2099FV】

●Switching characteristics (Unless otherwise specified, VDD=5V, VSS=0V, Ta=25℃)

Parameter Symbol

Limit

Unit

Condition

Min. Typ. Max. VDD(V)

Minimum Clock Pulse Width

(CLOCK)

t

W

1000 - - ns 3

-

500 - - ns 5

Minimum Latch Pulse Width

(LCK)

t

W

(LCK)

1000 - - ns 3

-

500 - - ns 5

Setup Time

(LCK→CLOCK)

t

S

400 - - ns 3

-

200 - - ns 5

Setup Time

(DATA→CLOCK)

t

su

400 - - ns 3

-

200 - - ns 5

Hole Time

(CLOCK→DATA)

t

H

400 - - ns 3

-

200 - - ns 5

Propagation

(SO)

t

PLH

t

PHL

- - 500 ns 3 -

- - 250 ns 5 -

Propagation

(LCK→QX) *

t

PLZ

(LCK)

- 360 - ns 3

RL=5kΩ

C

L=10pF

- 170 - ns 5

t

PZL

(LCK)

- 260 - ns 3 R

L=5kΩ

C

L=10pF

- 175 - ns 5

Propagation

(

QE

→QX) *

t

PLZ

- 115 - ns 3

R

L=5kΩ

C

L=10pF

- 85 - ns 5

t

PZL

- 175 - ns 3 R

L=5kΩ

C

L=10pF

- 65 - ns 5

Noise Pulse Suppression

Time (LCK) *

t

I

- 30 ns -

-

- 20 ns -

*Reference value

●Input Voltage Test Circuit

Fig. 8

●Switching Time Test Circuit

Fig. 9

RL =10kΩ

GND

(Vss)

P. G.

VIH

VIL

GND

RL =5kΩ

VDD

GND

(Vss)

P. G.

GND

(Vss)

C

L =10pF

+25V

RL =5kΩ

GND

(Vss)

CL =10pF

+25V

BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS

Technical Note

14/24

www.rohm.com

2009.06 - Rev.A

【BU2099FV】

●Output Voltage Test Circuit

Fig. 10

●Switching Time Test Waveforms

Fig. 11

VDD

GND

(Vss)

P. G.

GND

(Vss)

GND

(Vss)

GND

(Vss)

GND

(Vss)

GND

(Vss)

GND

(Vss)

IOL2IOH

SW4

1

2

±25V

SW2

1

2

3

SW1

1

12

SW3

Test condition

V

OL1 ：Set all data “L”. SW1=”ON”, SW2=”3”, SW3=”1”～”12”.

V

OL2 ：Set output data “L” to SO and SW4 is positioned to “2”, then voltage is measured at IOL2.

V

OH ：Set output data “H” to SO and SW4 is positioned to “1”, then voltage is measured at IOH.

CLOCK

DATA

t

SU

90%

10%

90% 90%

t

H

90% 90%

10%

90%

10%

t

W

t

W

50%

LCK

50%

90%

10%

t

S

90%

t

W

(CLK)

50%

OE

Qx

t

PLZ

t

PZL

(LCK)

10%

50%

10%

50%

t

PZL

V

DD

GND (V

SS

)

V

DD

GND (V

SS

)

V

DD

GND (V

SS

)

V

DD

GND (V

SS

)

V

EXT

GND (V

SS

)

50%

t

S

2

t

PLZ

(LCK)

SO

50%

t

PLH

t

PHL

V

DD

GND (V

SS

)

IOL1

BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS

Technical Note

15/24

www.rohm.com

2009.06 - Rev.A

【BD7851FP】

●Pin descriptions

Pin No. Pin Name Function

1 GND Ground

2 R_Iref Reference Current Output Current setting

3 LATCH Latch Signal Input

4 S_IN Serial Data Input

5～15

OUT16

～OUT6

Reference Current Output

16 P_GND Ground for Driver

17～21

OUT5

～OUT1

Reference Current Output

22 SOUT Serial Data Output

23 CLOCK Clock Input

24 ENABLE ENABLE

25 V

CC

V

CC

●Timing chart

Fig. 12

1. After the power is turned on and the voltage is stabilized, LATCH should be activated, after clocking 16 data bits

into the S_IN terminal.

2. OUTn parallel output data of the shift register is set after the 16

th

clock by the LATCH.

3. The final stage data of the shift register is outputted to the SOUT by synchronizing with the rise time of the

CLOCK.

4. Since the LATCH is a label latch, data is retained in the “L” section and renewed in the “H” section of the LATCH.

5. Data retained in the internal latch circuit is outputted when the ENABLE is in the “L” section. When the ENABLE

is in the “H” section, data is fixed in the “H” section.

CLOCK

LATCH

S_IN

DATA16 DATA15 DATA14 DATA2 DATA1

OUTn

Previous DATA DATA

SOUT

DATA16

DATA15 DATA14

ENABLE

BU2099FV-E2

BU2099FV-E2

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