BU2099FV-E2 Datasheet BU2152FS-E2, BU2092FV-E2, BU2099FV-E2 | P4-P6

BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS

Technical Note

4/24

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2009.06 - Rev.A

●Electrical characteristics

BD7851FP (Unless otherwise noted, Ta=25℃, V

CC

=5.0V)

Parameter Symbol Min. Typ. Max. Unit Condition

Power Supply Voltage VDD 4.5 - 5.5 V

Input high-level Voltage VIH

0.8×VCC

- - V

Input low-level Voltage VIL - - 0.2×VCC V

Output high-level Voltage VOH VCC-0.5 - - V

I

OH=-1mA

Output low-level Voltage VOL - - 0.5 V

IOL=1mA

Quiescent Current ICC

- 0.7 1.0 mA

R=13kΩ

OUT1～OUT16:OFF

- 1.8 3.0 mA

R=1.3kΩ

OUT1～OUT16:OFF

- 4.0 6.5 mA

R=13kΩ

OUT1～OUT16:ON

- 30 40 mA

R=1.3kΩ

OUT1～OUT16:ON

Reference Current Output Current

(including the equation between

each bit)

Iolc1 48 55 62 mA

VOUT=2.0V, R=1.3kΩ

Iolc2 5.0 5.9 6.8 mA VOUT=2.0V, R=13kΩ

Equation between each bit of

Reference Current Output Current

Δiolc - ±1 ±6 %

V

OUTn=2.0V, R=1.3kΩ

(1bit : ON)

Change rate of reference current

output current for output voltage

IΔV

CC - ±1 ±6 %/V

V

OUT=2.0 to 3.0V,

R=1.3kΩ

Output Leak Current IOH - 0.01 0.8 μA

VOUT=10V

BU2152FS (Unless otherwise noted, Ta=25℃, V

DD

=2.7 to 5.5V)

Parameter Symbol Min. Typ. Max. Unit Condition

Power Supply Voltage VDD 2.7 - 5.5 V

Input high-level Voltage VIH

2.0

- - V

V

DD=5V

Input low-level Voltage VIL - - 0.6 V

VDD=5V

Output high-level Voltage VOH

VDD-1.5 - -

V

IOH=-25mA

VDD-1.0 - -

I

OH=-15mA

VDD-0.5 - -

IOH=-10mA

Output low-level Voltage VOL

- - 1.5

V

IOL=25mA

- - 1.0

I

OL=15mA

- - 0.8

IOL=10mA

Quiescent Current IDDST - - 5 μA

V

IL=VSS, VIH=VDD

Input high-level Current IIH

-

- 1 μA

Input low-level Current IIL - - 1 μA

BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS

Technical Note

5/24

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2009.06 - Rev.A

●Block diagram

BU2050F

BU2092F/BU2092FV

BU2099FV

BD7851FP

BU2152FS

Controller

Shift

Register

STB

CLR

CLOCK

DAT

A

8bit

L

a

t

c

h

Write

Buffer

P1～P8

Controller

Shift

Register

LCK

CLOCK

DAT

A

12bit

L

a

t

c

h

Write

Buffer

Q0～Q11

OE

Controller

Shift

Register

LCK

CLOCK

DAT

A

12bit

L

a

t

c

h

Write

Buffer

Q0～Q11

OE

LPF

Shift

Register

S_IN

16bit

L

a

t

c

h

Write

Buffer

OUT1～OUT16

LATCH

CLOCK

Controller

Shift

Register

STB

CLB

CLOCK

DAT

A

24bit

L

a

t

c

h

Write

Buffer

P1～P24

SO

ENABLE

R_Ire

f

SOUT

Current Adjustment

BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS

Technical Note

6/24

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2009.06 - Rev.A

●Operating description

(1) Data clear

When the reset terminal (CLR, CLB) is set to “L”, the content of all latch circuits are set to “H”, and all parallel outputs are

initialised. (For model with reset terminal only)

(2) Data transfer

Serial data is sequentially input to the shift register during the rise of the clock time (strobe signal is not active). When

the strobe signal is active, the content of the shift register are transferred to the latch circuit.

(3) Cascade connection

Serial input data is output from the serial output through the shift register, regardless of the strobe signal.

(except for BU2050F,

BU2092F/BU2092FV)

●Application circuit

Fig. 1

●Interfaces

BU2050F BU2050F BU2092F/BU2092FV BU2092F/BU2092FV

DATA, CLOCK, STB, CLR P1～P8 DATA, CLOCK, LCK, OE Q0～Q11

BU2099FV BU2099FV BU2099FV BU2152FS

DATA, CLOCK, LCK, OE Q0～Q11 SO CLOCK, DATA, STB, CLB

BU2152FS BU2152FS

P1～P28 SO

VDD

Serial data input

Clock input

Strobe input

Latch input

P1 P2 Pn-2 Pn-1 Pn

Serial data outpu

t

VSS

P1 P2 Pn-2 Pn-1 Pn

VSS

VDD

VSS

MPU

C1

(*)

(*C1 must be placed as close to the terminal as possible.)

VDD

Serial data input

Clock input

Strobe input

Latch input

Serial data outpu

t

INPUT

GND(VSS)

V

DD

GND(VSS)

V

DD

OUTPUT

GND(VSS)

IN

GND(VSS)

V

DD

VDD

OUT

GND(VSS)

V

DD

OUT

GND(VSS)

VSS

V

DD VDD

VSS

GND(VSS)

V

DD VDD VDD

GND(VSS) GND(VSS)

GND(VSS)

V

DD VDD

GND(VSS)

VDD

GND(VSS)

VDD

GND(VSS)

VDD

GND(VSS)

VDD

IN

(only OE pin)

BU2099FV-E2

BU2099FV-E2

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