ADJD-J823 Datasheet ADJD-J823 | P10-P12

Calculating Sampling Frequency and PWM Output Frequency

The sampling frequency, f

SAMP

, which is the frequency at which ADJD-J823 samples the tricolor

photosensor, is related to the system clock frequency, f

CLK

. The output PWM frequency, f

PWM

, is

also related to f

CLK

Calculation example:

SAMPFREQ x 8

CLK

SAMP

= 108Hz(nominal)

(PWMFREQ + 1) x 4096

CLK

PWM

= 6.35kHz(nominal)

CLK

= 26 MHz (nominal)

SAMPFREQ = Sampling frequency register setting = concatenation of registers [0x06][0x07]

PWMFREQ = PWM frequency register setting = register [0x05]

The internal oscillator frequency varies from part-to-part but it will not vary as significantly

during operation.

Color drift over temperature

Data obtain from 5 units. Color set point is at 9000K and V

DDD

& V

DDA

at 2.6V.

System consists of ADJD-J823 and RGB LEDs with color coordinates, Red (x,y) = (0.691, 0.309),

Green (x,y) = (0.161, 0.704), Blue (x,y) = (0.131, 0.073). The R:G:B luminance ratio is 2.6 : 3.9 : 1.0

Color drift

0.001

0.002

0.003

0.004

0.005

0.006

0.007

0.008

0.009

0 102030405060

System temperature (˚C)

du'v'

Note: The starting point is at 25

C and is zero color drift as all measurements are made relative to the starting point at 25

Figure 2. START/STOP Condition

START condition

STOP condition

SDA

SCL

Serial Interface Reference

Description

The programming interface to the ADJD-J823 is a 2-wire serial bus. The bus consists of a serial

clock (SCL) and a serial data (SDA) line. The SDA line is bi-directional on ADJD-J823 and must

be connected through a pull-up resistor to the positive power supply. When the bus is free, both

lines are HIGH.

The 2-wire serial bus on ADJD-J823 requires one device to act as a master while all other

devices must be slaves. A master is a device that initiates a data transfer on the bus, generates

the clock signal and terminates the data transfer while a device addressed by the master is called

a slave. Slaves are identified by unique device addresses.

Both master and slave can act as a transmitter or a receiver but the master controls the direction

for data transfer. A transmitter is a device that sends data to the bus and a receiver is a device

that receives data from the bus.

The ADJD-J823 serial bus interface always operates as a slave transceiver with a data transfer

rate of up to 100kbit/s.

START/STOP Condition

The master initiates and terminates all serial data transfers. To begin a serial data transfer, the

master must send a unique signal to the bus called a START condition. This is defined as a HIGH

to LOW transition on the SDA line while SCL is HIGH.

The master terminates the serial data transfer by sending another unique signal to the bus called

a STOP condition. This is defined as a LOW to HIGH transition on the SDA line while SCL is

HIGH.

The bus is considered to be busy after a START (S) condition. It will be considered free a certain

time after the STOP (P) condition. The bus stays busy if a repeated START (Sr) is sent instead of

a STOP condition.

The START and repeated START conditions are functionally identical.

Data Transfer

The master initiates data transfer after a START condition. Data is transferred in bits with the

master generating one clock pulse for each bit sent. For a data bit to be valid, the SDA data line

must be stable during the HIGH period of the SCL clock line. Only during the LOW period of the

SCL clock line can the SDA data line change state to either HIGH or LOW.

Figure 3. Data Bit Transfer

SDA

SCL

Data valid Data change

The SCL clock line synchronizes the serial data transmission on the SDA data line. It is always

generated by the master. The frequency of the SCL clock line may vary throughout the

transmission as long as it still meets the minimum timing requirements.

The master by default drives the SDA data line. The slave drives the SDA data line only when

sending an acknowledge bit after the master writes data to the slave or when the master requests

the slave to send data.

The SDA data line driven by the master may be implemented on the negative edge of the SCL

clock line. The master may sample data driven by the slave on the positive edge of the SCL clock

line. Figure 4 shows an example of a master implementation and how the SCL clock line and

SDA data line can be synchronized.

SDA

SCL

SDA data sampled on the

positive edge of SCL

SDA data driven on the

negative edge of SCL

Figure 4. Data Bit Synchronization

Figure 5. Data Byte Transfer

SDA

SCL

MSB LSB

12 89

ACK

12 8

ACK

START or repeated

START condition

STOP or repeated

START condition

MSB LSB

A complete data transfer is 8-bits long or 1-byte. Each byte is sent the most significant bit (MSB)

first followed by an acknowledge or not acknowledge bit. Each data transfer can send an

unlimited number of bytes (depending on the data format).

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

ADJD-J823

Mfr. #:

Buy ADJD-J823

Manufacturer:

Broadcom / Avago

Description:

LED Lighting Modules Color Controller

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet

ADJD-J823