8531-01 Data Sheet
©2016 Integrated Device Technology, Inc Revision F January 19, 201613
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
– 0.9V
(V
CCO_MAX
- V
OH_MAX
)
= 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
– 1.7V
(V
CCO_MAX
- V
OL_MAX
)
= 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))
/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))
/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
8531-01 Data Sheet
©2016 Integrated Device Technology, Inc Revision F January 19, 201614
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for 8531-01 is: 632
TABLE 7. θ
JA
VS. AIR FLOW TABLE FOR 32 LEAD LQFP
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8531-01 Data Sheet
©2016 Integrated Device Technology, Inc Revision F January 19, 201615
PACKAGE OUTLINE AND DIMENSIONS - Y SUFFIX FOR 32 LEAD LQFP
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
BBA
MINIMUM NOMINAL MAXIMUM
N
32
A
-- -- 1.60
A1
0.05 -- 0.15
A2
1.35 1.40 1.45
b
0.30 0.37 0.45
c
0.09 -- 0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
e
0.80 BASIC
L
0.45 0.60 0.75
θ
0°
--
7°
ccc
-- -- 0.10
TABLE 8. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-026

8531AY-01LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 1-to-9 LVPECL Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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