8531-01 Data Sheet
©2016 Integrated Device Technology, Inc Revision F January 19, 201617
REVISION HISTORY SHEET
Rev Table Page Description of Change Date
B
4A
4C
4D
5
4
4
5
5
Separated LVCMOS rows into own table.
Changed HSTL table to Differential table.
Changed V
PP
value from 0.1 Min. to 0.15 Min.0Changed V
CMR
values from 0.13 Min, 1.3
Max. to 0.5 Min,
V
CC
- 0.85.
In LVPECL table, changed V
CMR
values from 0.7 Min, 2.5 Max. to 0.5 Min,
V
CC
- 0.85.
Changed V
OH
values from 1.9 Min., 2.3 Max. to V
CC
- 1.4 Min., V
CC
- 1.0 Max.
Changed V
OL
values from 1.2 Min, 1.6 Max. to V
CC
- 2.0 Min, V
CC
- 1.7 Max.
Changed V
SWING
values from 0.55 Min. to 0.6 Min.
Changed tp
LH
& tp
HL
rows to t
PD
. Values stayed same.
t
R
and t
F
values changed from 100 Min, 600 Max. to 300 Min., 700 Max.
Changed t
DC
row to odc. Values stayed same.
Deleted t
S
and t
H
rows.
6/15/01
B1
Changed all V
DDx
to V
CCx
.
Changed V
CCO
to equal 3.3V ± 5% from 1.8V ± 0.2V.
Updated Block Diagram.
6/18/01
B
4C
4D
4
5
Changed V
CMR
value from 0.5 Min. to V
EE
+ 0.5 Min.
Changed V
PP
values from 0.15 Min, 1.3 Max, to 03. Min, 1 Max.
Changed V
CMR
values from 0.5 Min., V
CC
- 0.85 Max. to V
EE
+ 1.5 Min., V
CC
Max.
8/9/01
B
3
6
6, 7
Udated Figure 1, CLK_EN Timing Diagram.
Updated Figure 2, Output Load Test Circuit.
Revised labels on fi gures.
11/1/01
B
8 Added Termination for LVPECL Outputs section.
5/28/02
B
2
4
5
Pin Description table - V
CC
description changed to “Core supply pin” from
“Positive supply pin”.
Power Supply Characteristics table - V
CC
description changed to
“Core Supply Voltage” from “Positive Supply Voltage”.
Output Load Test Circuit diagram - corrected V
EE
equation to read,
V
EE
= -1.3V ± 0.165V from V
EE
= -1.3V ± 0.135V.
10/02/02
C
T2
T4A
2
4
4
7
8
9
10
Pin Characteristics table - changed C
IN
4pF max. to 4pF typical.
Updated Absolute Maximum Ratings.
Power Supply DC Characteristics table - changed I
EE
70mA max. to 80mA max and
deleted 50mA typical.
Updated LVPECL Output Termination drawings.
Added Differential Clock Input Interface section.
Added LVPECL Clock Input Interface section.
Power Considerations - corrected Power Dissipation from 70mA to 80mA to corre-
spond with I
EE
.
Updated format throughout the data sheet.
2/2/04
C
T9 14 Ordering Information Table - added Lead-Free part number.
10/15/04
D
T4D
T9
5
7
15
LVPECL DC Characteristics - changed VSWING max. limit from 850mV to 1.0V.
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added lead-free note.
6/23/06
E
1
T5 5
6
Features Section - added RMS Phase Jitter bullet.
AC Characteristics Table - add RMS Phase Jitter spec.
Added Additve Phase Jitter Plot.
12/4/06
F
T4D 5
12 - 13
LVPECL DC Characteristics Table -corrected V
OH
max. from V
CCO
- 1.0V to
V
CCO
- 0.9V.
Power Considerations - corrected power dissipation to refl ect V
OH
max in Table 4D.
4/11/07
F
T9
1
1
16
Removed ICS from the part number where needed.
General Description - Removed ICS Chip and Hiperclocks.
Features section - removed reference to leaded part.
Ordering Information - removed quantity from tape and reel. Deleted LF note below
the table.
Updated header and footer.
1/19/16
