6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore Industrial and Commercial Temperature Ranges
2
2721 drw 02
IDT71342J
J52-1
(4)
52-Pin PLCC
Top View
(5)
INDEX
N
/
C
G
N
D
I
/
O
4
L
I
/
O
5
L
I
/
O
6
L
I
/
O
7
L
I
/
O
0
R
I
/
O
1
R
I
/
O
2
R
I
/
O
3
R
I
/
O
4
R
I
/
O
5
R
I
/
O
6
R
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
N/C
I/O
7R
46
45
44
43
42
41
40
39
38
37
36
35
34
I/O
3L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
8
9
10
11
12
13
14
15
16
17
18
19
20
474849505152
1
234567
33323130292827262524232221
S
E
M
L
A
0
L
V
C
C
O
E
L
R
/
W
L
C
E
R
R
/
W
R
C
E
L
A
1
0
L
A
1
1
L
A
1
0
R
A
1
1
R
S
E
M
R
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52 package body is approximately .79 in x .79 in x .17 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Configurations
(1,2,3)
INDEX
71342PF
PN64-1
(4)
64-Pin TQFP
Top View
(5)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33
1
7
1
8
1
9
2
0
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
4
9
5
0
5
1
5
2
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
6
4
I/O
6R
N/C
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
OE
R
N/C
N/C
I/O
2L
A
0L
OE
L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
N/C
N/C
I
/
O
4
L
I
/
O
5
L
I
/
O
6
L
I
/
O
7
L
I
/
O
0
R
I
/
O
1
R
I
/
O
2
R
I
/
O
3
R
I
/
O
4
R
I
/
O
5
R
I
/
O
3
L
N
/
C
N
/
C
G
N
D
N
/
C
N
/
C
A
1
0
R
V
C
C
C
E
R
C
E
L
N
/
C
N
/
C
A
1
0
L
N
/
C
N
/
C
N
/
C
A
1
1
L
A
1
1
R
2721 drw 03
S
E
M
L
R
/
W
L
S
E
M
R
R
/
W
R
Description
The IDT71342 is a high-speed 4K x 8 Dual-Port Static RAM with full
on-chip hardware support of semaphore signalling between the two
ports.
The IDT71342 provides two independent ports with separate
control, address, and I/O pins that permit independent, asynchronous
access for reads or writes to any location in memory. To assist in
arbitrating between ports, a fully independent semaphore logic block
is provided. This block contains unassigned flags which can be
accessed by either side; however, only one side can control the flag at any
time. An automatic power down feature, controlled by CE and SEM,
permits the on-chip circuitry of each port to enter a very low standby power
mode (both CE and SEM HIGH).
Fabricated using CMOS high-performance technology, this device
typically operates on only 700mW of power. Low-power (LA) versions
offer battery backup data retention capability, with each port typically
consuming 200µW from a 2V battery. The device is packaged in either a
64-pin TQFP or a 52-pin PLCC.
