6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore Industrial and Commercial Temperature Ranges
6
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(5)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Ouput Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access SRAM, CE = V
IL, SEM = VIH. To access semaphore, CE = VIH, and SEM = VIL.
4. 'X' in part number indicates power rating (SA or LA).
5. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
71342X20
Com'l Only
71342X25
Com'l & Ind
71342X35
Com'l Only
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cycle Time 20
____
25
____
35
____
ns
t
AA
Address Access Time
____
20
____
25
____
35 ns
t
ACE
Chip Enable Access Time
(3)
____
20
____
25
____
35 ns
t
AOE
Output Enable Access Time
____
15
____
15
____
20 ns
t
OH
Output Hold from Address Change 0
____
0
____
0
____
ns
t
LZ
Output Low-Z Time
(1,2)
0
____
0
____
0
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
15
____
20 ns
t
PU
Chip Enable to Power Up Time
(2)
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2)
____
50
____
50
____
50 ns
t
SOP
SEM Flag Update Pulse (OE or SEM)
10
____
10
____
15
____
ns
t
WDD
Write Pulse to Data Delay
(4)
____
40
____
50
____
60 ns
t
DDD
Write Data Valid to Read Data Delay
(4)
____
30
____
30
____
35 ns
t
SAA
Semaphore Address Access Time
____ ____ ____
25
____
35 ns
2721 tbl 09a
71342X45
Com'l Only
71342X55
Com'l Only
71342X70
Com'l Only
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cycle Time 45
____
55
____
70
____
ns
t
AA
Address Access Time
____
45
____
55
____
70 ns
t
ACE
Chip Enable Access Time
(3)
____
45
____
55
____
70 ns
t
AOE
Output Enable Access Time
____
25
____
30
____
40 ns
t
OH
Output Hold from Address Change 0
____
0
____
0
____
ns
t
LZ
Outp ut Low-Z Time
(1,2)
5
____
5
____
5
____
ns
t
HZ
Output High-Z Time
(1,2)
____
20
____
25
____
30 ns
t
PU
Chip Enable to Power Up Time
(2)
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2)
____
50
____
50
____
50 ns
t
SOP
SEM Flag Update Pulse (OE or SEM)
15
____
20
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(4)
____
70
____
80
____
90 ns
t
DDD
Write Data Valid to Read Data Delay
(4)
____
45
____
55
____
70 ns
t
SAA
Semaphore Address Access Time
____
45
____
55
____
70 ns
2721 tbl 09b
