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71342SA25PF

P1-P3P4-P6P7-P9P10-P12P13-P14
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore Industrial and Commercial Temperature Ranges
7
Timing Waveform of Read Cycle No. 1, Either Side
(1,2,4)
NOTES:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2. CE
L = CER = VIL. CE"B" = VIL.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
Timing Waveform of Read Cycle No. 2, Either Side
(1,3)
Timing Waveform of Write with Port-to-Port Read
(2,3)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = V
IH and OE = VIL, unless otherwise noted.
4. Start of valid data depends on which timing becomes effective last; t
AOE, tACE, or tAA
5. To access SRAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tAA is for SRAM Address Access and tSAA is for Semaphore Address Access.
t
AA or
t
SAA
ADDRESS
DATA
OUT
PREVIOUS DATA VALID DATA VALID
t
OH
t
OH
t
RC
2721 drw 07
2721 drw 08
CE or SEM
DATA
OUT
VALID DATA
t
PD
t
AOE
t
ACE
OE
t
HZ
t
LZ
t
LZ
t
PU
50%50%
I
CC
I
SB
CURRENT
t
HZ
t
SOP
(5)
t
SOP
(1)
(1)
(4)
(2)
(2)
(4)
2721 drw 09
R/W
"A"
VALID
t
WC
MATCH
VALID
MATCH
t
WP
t
DW
t
WDD
t
DDD
ADDR
"A"
DATA
IN "A"
DATA
OUT "B"
ADDR
"B"
(1)
t
DH
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore Industrial and Commercial Temperature Ranges
8
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage
(5)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
3. To access SRAM, CE = V
IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for t
DH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual t
DH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (SA or LA).
Symbol Parameter
71342X20
Com'l Only
71342X25
Com'l & Ind
71342X35
Com'l Only
UnitMin. Max. Min. Max. Min. Max.
WRIT E CYCL E
t
WC Write Cycle Time 20
____
25
____
35
____
ns
t
EW Chip Enable to End-of-Write
(3)
15
____
20
____
30
____
ns
t
AW Address Valid to End-of-Write 15
____
20
____
30
____
ns
t
AS Address Set-up Time 0
____
0
____
0
____
ns
t
WP Write Pulse Width 15
____
20
____
25
____
ns
t
WR Write Recovery Time 0
____
0
____
0
____
ns
t
DW Data Valid to End-of-Write 15
____
15
____
20
____
ns
t
HZ Output High-Z Time
(1,2)
____
15
____
15
____
20 ns
t
DH Data Hold Time
(4)
0
____
0
____
3
____
ns
t
WZ Write Enable to Output in High-Z
(1,2)
____
15
____
15
____
20 ns
t
OW Output Ac tive from End -of-Write
(1,2,4)
3
____
3
____
3
____
ns
t
SWR
SEM Flag Write to Read Time
10
____
10
____
10
____
ns
t
SPS
SEM Flag Contention Window
10
____
10
____
10
____
ns
2721 tbl 10a
Symbol Parameter
71342X45
Com'l Only
71342X55
Com'l Only
71342X70
Com'l Only
UnitMin. Max. Min. Max. Min. Max.
WRIT E CYCL E
t
WC Write Cycle Time 45
____
55
____
70
____
ns
t
EW Chip Enable to End-of-Write
(3)
40
____
50
____
60
____
ns
t
AW Address Valid to End-of-Write 40
____
50
____
60
____
ns
t
AS Address Set-up Time 0
____
0
____
0
____
ns
t
WP Write Pulse Width 40
____
50
____
60
____
ns
t
WR Write Recovery Time 0
____
0
____
0
____
ns
t
DW Data Valid to End-of-Write 20
____
25
____
30
____
ns
t
HZ Output High-Z Time
(1,2)
____
20
____
25
____
30 ns
t
DH Data Hold Time
(4)
3
____
3
____
3
____
ns
t
WZ Write Enable to Output in High-Z
(1,2)
____
20
____
25
____
30 ns
t
OW Output Ac tive from End -of-Write
(1,2,4)
3
____
3
____
3
____
ns
t
SWR
SEM Flag Write to Read Time
10
____
10
____
10
____
ns
t
SPS
SEM Flag Contention Window
10
____
10
____
10
____
ns
2721 tbl 10b
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore Industrial and Commercial Temperature Ranges
9
CE or SEM
2721 drw 10
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
R/W
t
WP
t
DH
DATA
OUT
t
WZ
(4)
(4)
t
OW
OE
t
HZ
t
LZ
t
HZ
(9)
(6)
(7)
(2)
(3)
(7)
(7)
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING
(1,5,8)
Timing Waveform of Write Cycle No. 2, CE Controlled Timing
(1, 5)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW or tWP) of either CE or SEM = VIL and R/W = VIL.
3. t
WR is measured from the earlier of CE or R/W going HIGH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
WP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus
for the required t
DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access SRAM, CE =V
IL
and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
2721 drw 11
R/W
t
WC
ADDRESS
DATA
IN
CE or SEM
t
DW
t
WR
t
DH
t
EW
t
AS
t
AW
(9)
(6)
(2)
(3)
P1-P3P4-P6P7-P9P10-P12P13-P14

71342SA25PF

Mfr. #:
Buy 71342SA25PF
Manufacturer:
IDT
Description:
SRAM 32K (4KX8) CMOS DUAL PORT
Lifecycle:
New from this manufacturer.
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