Table 1. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
Table 2. Channel Selection in Pseudo-Differential Mode (SGL/DIF = 0)
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
12 ______________________________________________________________________________________
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, the difference of
[(
IN+) - (IN-)
]
is con-
verted. At the end of the conversion, the positive input
connects back to IN+ and C
HOLD
charges to the input
signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
t
ACQ
, is the maximum time the device takes to acquire
the signal and the minimum time needed for the signal
to be acquired. It is calculated by the following equa-
tion:
t
ACQ
= 9
✕
(R
S
+ R
IN
)
✕
18pF
where R
IN
= 800Ω and R
S
= the source impedance of
the input signal; t
ACQ
is never less than 400ns
(MAX1282) or 625ns (MAX1283). Note that source
impedances below 2kΩ do not significantly affect the
ADC’s AC performance.
Input Bandwidth
The ADC’s input tracking circuitry has a 6MHz
(MAX1282) or 3MHz (MAX1283) small-signal band-
width, so it is possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using under-
sampling techniques. To avoid high-frequency signals
being aliased into the frequency band of interest, anti-
alias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog input
to V
DD1
and GND, allow the channel input pins to swing
from GND - 0.3V to V
DD1
+ 0.3V without damage.
However, for accurate conversions near full scale, the
inputs must not exceed V
DD1
by more than 50mV or be
lower than GND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not allow the input current to exceed 2mA.
Starting a Conversion
Start a conversion by clocking a control byte into DIN.
With CS low, each rising edge on SCLK clocks a bit from
DIN into the MAX1282/MAX1283’s internal shift register.
After CS falls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 3 shows the control-byte format.
The MAX1282/MAX1283 are compatible with SPI/
QSPI/MICROWIRE devices. For SPI, select the correct
clock polarity and sampling edge in the SPI control reg-
isters: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI,
and QSPI all transmit a byte and receive a byte at the
same time. Using the Typical Operating Circuit, the sim-
plest software interface requires only three 8-bit transfers
to perform a conversion (one 8-bit transfer to configure
the ADC, and two more 8-bit transfers to clock out the
SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 COM
00 1+ –
10 1 + –
01 0 + –
11 0 + –
SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3
00 1+–
01 0 +–
10 1–+
11 0 –+
