MAX1282BCUE+ Datasheet MAX1282BEUE+, MAX1282BCUE+, MAX1283BEUE+ | P16-P18

MAX1282/MAX1283

Using Fast Power-Down

and Reduced-Power Modes

FASTPD and REDP modes achieve the lowest power

consumption at speeds close to the maximum sampling

rate. Figure 10 shows the MAX1283’s power

consumption in FASTPD mode (PD1 = 0, PD0 = 1),

REDP mode (PD1 = 1, PD0 = 0), and, for comparison,

normal operating mode (PD1 = 1, PD0 = 1). The figure

shows power consumption using the specified power-

down mode, with the internal reference and conversion

controlled at the maximum clock speed. The clock

speed in FASTPD or REDP should be limited to 4.8MHz

for the MAX1282/MAX1283. FULLPD mode may provide

increased power savings in applications where the

MAX1282/MAX1283 are inactive for long periods of time,

but intermittent bursts of high-speed conversions are

required. Figure 11b shows FASTPD and REDP timing.

Internal and External References

The MAX1282/MAX1283 can be used with an internal

or external reference voltage. An external reference

can be connected directly at REF or at the REFADJ pin.

An internal buffer is designed to provide 2.5V at

REF for the MAX1282/MAX1283. The internally trimmed

1.22V reference is buffered with a 2.05 gain.

Internal Reference

The MAX1282/MAX1283’s full-scale range with the inter-

nal reference is 2.5V with unipolar inputs and ±1.25V

with bipolar inputs. The internal reference voltage is

adjustable by ±100mV with the circuit in Figure 12.

External Reference

The MAX1282/MAX1283’s external reference can be

placed at the input (REFADJ) or the output (REF) of the

internal reference-buffer amplifier. The REFADJ input

impedance is typically 17kΩ. At REF, the DC input

resistance is a minimum of 18kΩ. During conversion, an

external reference at REF must deliver up to 350µA DC

load current and have 10Ω or less output impedance. If

the reference has a higher output impedance or is

noisy, bypass it close to the REF pin with a 4.7µF

capacitor.

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

16 ______________________________________________________________________________________

SCLK

DIN

DOUT

SSTRB

CSS

CSO

DOE

STE

CSW

CSH

CS1

STD

DOD

DOV

DOH

STV

STH

#10

Figure 6. Detailed Serial-Interface Timing

UNIPOLAR MODE BIPOLAR MODE

Full Scale Zero Scale

Positive Zero Negative

Full Scale Scale Full Scale

Table 5. Full Scale and Zero Scale

REF

+ V

COM

REF

/ 2

+ V

COM

REF

/ 2

+ V

COM

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

______________________________________________________________________________________ 17

SCLK

11 15885812 12 1216 16 1 516

B6B11B0B6B11B0

DIN

SSTRB

DOUT

CONTROL BYTE 0SSSCONTROL BYTE 1

CONVERSION RESULT 1CONVERSION RESULT 0

CONTROL BYTE 2 S ETC

B6B11

Figure 7. Continuous 16-Clock/Conversion Timing

0.50

0.25

1.00

0.75

1.25

1.50

0.0001 0.010.001 0.1 1 10

TIME IN SHUTDOWN (s)

REFERENCE POWER-UP DELAY (ms)

MAX1283, V

DD1

DD2

3.0V

LOAD

= 20pF

CODE = 101010000000

100

0.1 101 100 1k 10k

SAMPLING RATE (sps)

SUPPLY CURRENT (µA)

4 CHANNELS

1 CHANNEL

10k

100

110010 1k 10k 100k

SAMPLING RATE (sps)

SUPPLY CURRENT (µA)

MAX1283, V

DD1

DD 2

3.0V

LOAD

= 20pF

CODE = 101010000000

4 CHANNELS

1 CHANNEL

Figure 8. Reference Power-Up Delay vs. Time in Shutdown

Figure 9a. Average Supply Current vs. Conversion Rate with

Internal Reference in FULLPD

Figure 9b. Average Supply Current vs. Conversion Rate with

External Reference in FULLPD

2.5

2.0

1.0

1.5

0.5

150

250

100

200

300 350

SAMPLING RATE (sps)

SUPPLY CURRENT (mA)

MAX1283, V

DD1

DD2

3.0V

LOAD

= 20pF

CODE = 101010000000

REDP

FASTPD

NORMAL OPERATION

Figure 10. Average Supply Current vs. Sampling Rate (in

FASTPD, REDP, and Normal Operation)

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

18 ______________________________________________________________________________________

Figure 11a. Full Power-Down Timing

RE FADJ

1.22V

2.5mA

1.3mA OR 0.9mA

DIN

VDD1

+ I

VDD2

REF

FULLPD

REDP

WAIT 2ms (10 x RC)

FULLPD

γ = RC = 17kΩ x 0.01µF

DUMMY CONVERSION

2.5V

2.5mA

0mA

2.5V

Figure 11b. FASTPD and REDP Timing

2.5V (ALWAYS ON)

2.5mA

DIN

DD1

+ IV

DD2

REF

REDP

REDP FASTPD

2.5mA

0.9mA

1.3mA

To use the direct REF input, disable the internal buffer by

connecting REFADJ to V

DD1

. Using the REFADJ input

makes buffering the external reference unnecessary.

Transfer Function

Table 5 shows the full-scale voltage ranges for unipolar

and bipolar modes.

Figure 13 depicts the nominal, unipolar input/output

(I/O) transfer function, and Figure 14 shows the bipolar

I/O transfer function. Code transitions occur halfway

between successive-integer LSB values. Output coding

is binary, with 1LSB = 0.61mV (2.500V / 4096) for unipo-

lar operation, and 1LSB = 0.61mV [(2.500V / 2) / 4096]

for bipolar operation.

Layout, Grounding, and Bypassing

For best performance, use PC boards; wire-wrap

boards are not recommended. Board layout should

ensure that digital and analog signal lines are separated

from each other. Do not run analog and digital (espe-

cially clock) lines parallel to one another, or digital lines

underneath the ADC package.

Figure 15 shows the recommended system ground

connections. Establish a single-point analog ground

(star ground point) at GND. Connect all other analog

grounds to the star ground. Connect the digital system

ground to this ground only at this point. For lowest-

noise operation, the ground return to the star ground’s

power supply should be low impedance and as short

as possible.

High-frequency noise in the V

DD1

power supply may

affect the high-speed comparator in the ADC. Bypass

the supply to the star ground with 0.1µF and 10µF

capacitors close to V

DD1

of the MAX1282/MAX1283.

Minimize capacitor lead lengths for best supply-noise

rejection. If the power supply is very noisy, a 10Ω resis-

tor can be connected as a lowpass filter (Figure 15).

High-Speed Digital Interfacing with QSPI

The MAX1282/MAX1283 can interface with QSPI using

the circuit in Figure 16 (CPOL = 0, CPHA = 0). This

QSPI circuit can be programmed to do a conversion on

each of the four channels. The result is stored in memory

without taxing the CPU, since QSPI incorporates its own

microsequencer.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

MAX1282BCUE+

Mfr. #:

Buy MAX1282BCUE+

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 12-Bit 4Ch 400ksps 5.5V Precision ADC

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MAX1282BCUE+

MAX1282BCUE+

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