AD669SQ Datasheet AD669BRZ, AD669ARZ, AD669BNZ | P10-P12

AD669

REV. A

–9–

Unipolar coding is straight binary, where all zeros (0000H) on

the data inputs yields a zero analog output and all ones

(FFFFH) yields an analog output 1 LSB below full scale.

Bipolar coding is offset binary, where an input code of 0000H

yields a minus full-scale output, an input of FFFFH yields an

output 1 LSB below positive full scale, and zero occurs for an

input code with only the MSB on (8000H).

The AD669 can be used with twos complement input coding if

an inverter is used on the MSB (DB15).

DIGITAL INPUT CONSIDERATIONS

The threshold of the digital input circuitry is set at 1.4 volts.

The input lines can thus interface with any type of 5 volt logic.

The AD669 data and control inputs will float to indeterminate

logic states if left open. It is important that

CS and L1 be con-

nected to DGND and Chat LDAC be tied to V

if these pins

are not used.

Fanout for the AD669 is 40 when used with a standard low

power Schottky gate output device.

16-BIT MICROPROCESSOR INTERFACE

The 16-bit parallel registers of the AD669 allow direct interfac-

ing to 16-bit general purpose and DSP microprocessor buses.

The following examples illustrate typical AD669 interface

configurations.

AD669 TO ADSP-2101 INTERFACE

The flexible interface of the AD669 minimizes the required

“glue” logic when it is connected in configurations such as the

one shown in Figure 8. The AD669 is mapped into the ADSP-

2101’s memory space and requires two wait states using a 12.5

MHz processor clock.

In this configuration, the ADSP-2101 is set up to use the inter-

nal timer to interrupt the processor at the desired sample rate.

The

WR pin and data lines D8–D23 from the ADSP-2101 are

tied directly to the

L1 and DB0 through DB15 pins of the

AD669, respectively. The decoded signal

CS1 is connected to

both

CS and LDAC. When a timer interrupt is detected, the

ADSP-2101 automatically vectors to the appropriate service

routine with minimal overhead. The interrupt routine then in-

structs the processor to execute a data memory write to the ad-

dress of the AD669.

The

WR pin and CS1 both go low causing the first 16-bit latch

inside the AD669 to be transparent. The data present in the first

rank is then latched by the rising edge of

WR. The rising edge

CS1 will cause the second rank 16-bit latch to become

transparent updating the output of the DAC. The length of

WR is extended by two wait states to comply with the timing

requirements of t

LOW

shown in Figure 1b. It is important to

latch the data with the rising edge of

WR rather than the decoded

CS1. This is necessary to comply with the t

specification of

the AD669.

ADSP-2101

DGND

+5V

DECODER

ADDRESS BUS

LDAC

AD669

DGNDDB0

DATA BUS

DMS

CS1

A13

DB15

D23

OUT

a. ADSP-2101 to AD669 Interface

A13

A12

A11

DMS

CS1

b. Typical Address Decoder

Figure 8. ADSP-2101 to AD669 Interface

Figure 8b shows the circuitry a typical decoder might include.

In this case, a data memory write to any address in the range

3000H to 3400H will result in the AD669 being updated. These

decoders will vary greatly depending on the number of devices

memory-mapped by the processor.

AD669 TO DSP56001 INTERFACE

Figure 9 shows the interface between the AD669 and the

DSP56001. Like the ADSP-2101, the AD669 is mapped into

the DSP56001’s memory space. This application was tested

with a processor clock of 20.48 MHz (t

CYC

= 97.66 ns) although

faster rates are possible.

An external clock connected to the

IRQA pin of the DSP56001

interrupts the processor at the desired sample rate. If ac perfor-

mance is important, this clock should be synchronous with the

DSP56001 processor clock. Asynchronous clocks will cause jit-

ter on the latch signal due to the uncertainty associated with the

acknowledgment of the interrupt. A synchronous clock is easily

generated by dividing down the clock from the DSP crystal. If

ac performance is not important, it is not necessary for

IRQA to

be synchronous.

After the interrupt is acknowledged, the interrupt routine ini-

tiates a memory write cycle. All of the AD669 control inputs are

AD669

REV. A

–10–

tied together which configures the input stage as an edge trig-

gered 16-bit register. The rising edge of the decoded signal

latches the data and updates the output of the DAC. It is neces-

sary to insert wait states after the processor initiates the write

cycle to comply with the timing requirements t

LOW

shown in

Figure 1b. The number of wait states that are required will vary

depending on the processor cycle time. The equation given in

Figure 9 can be used to determine the number of wait states

given the frequency of the processor crystal.

A0–A15

DSP56001

D0–D23

DGND

+5V

EXTERNAL

CLOCK

ADDRESS

DECODE

74F32

LDAC

AD669

DGND

DB0–DB15

XTAL

X/Y

IRQA

CS1

T =

2 (XTAL)

t – T + 9ns

LOW

# OF

WAIT STATES =

Figure 9. DSP56001 to AD669 Interface

As an example, the 20.48 MHz crystal used in this application

results in T = 24.4 ns which means that the required number of

wait states is about 2.76. This must be rounded to the next

highest integer to assure that the minimum pulse widths comply

with those required by the AD669. As the speed of the proces-

sor is increased, the data hold time relative to

CS1 decreases. As

processor clocks increase beyond 20.48 MHz, a configuration

such as the one shown for the ADSP-2101 is the better choice.

AD669 TO 8086 INTERFACE

Figure 10 shows the 8086 16-bit microprocessor connected to

multiple AD669s. The double-buffered capability of the AD669

allows the microprocessor to write to each AD669 individually

and then update all the outputs simultaneously. Processor

speeds of 6, 8, and 10 MHz require no wait states to interface

with the AD669.

The 8086 software routine begins by writing a data word to the

CS1 address. The decoder must latch the address using the

ALE signal. The decoded

CS1 pulse goes low causing the first

rank latch of the associated AD669 to become transparent.

Simultaneously, the 8086 places data on the multiplexed bus

which is then latched into the first rank of the AD669 with the

rising edge of the

WR pulse. Care should be taken to prevent

excessive delays through the decoder potentially resulting in a

violation of the AD669 data hold time (t

The same procedure is repeated until all three AD669s have had

their first rank latches loaded with the desired data. A final write

command to the LDAC address results in a high-going pulse

that causes the second rank latches of all the AD669s to become

transparent. The falling edge of LDAC latches the data from the

first rank until the next update. This scheme is easily expanded

to include as many AD669s as required.

8086

DGND

+5V

ALE

ADDRESS

DECODE

LDAC

CS1 CS2 CS3

DGND

DB0 – DB15

LDAC

AD669

OUT

AD0 – AD15

DGND

DB0 – DB15

LDAC

AD669

OUT

DGND

DB0 – DB15

LDAC

AD669

OUT

Figure 10. 8086-to-AD669 Interface

8-BIT MICROPROCESSOR INTERFACE

The AD669 can easily be operated with an 8-bit bus by the ad-

dition of an octal latch. The 16-bit first rank register is loaded

from the 8-bit bus as two bytes. Figure 11 shows the configura-

tion when using a 74HC573 octal latch.

The eight most significant bits are latched into the 74HC573 by

setting the “latch enable” control line low. The eight least sig-

nificant bits are then placed onto the bus. Now all sixteen bits

can be simultaneously loaded into the first rank register of the

AD669 by setting

CS and L1 low.

8-BIT µP

AND

CONTROL

74HC573

LDAC

MSB

DB8

DB7

LSB

AD669

CS1 L1

Figure 11. Connections for 8-Bit Bus Interface

AD669

REV. A

–11–

NOISE

In high resolution systems, noise is often the limiting factor. A

16-bit DAC with a 10 volt span has an LSB size of 153 µV

(–96 dB). Therefore, the noise floor must remain below this

level in the frequency range of interest. The AD669’s noise

spectral density is shown in Figures 12 and 13. Figure 12 shows

the DAC output noise voltage spectral density for a 20 V span

excluding the reference. This figure shows the l/f corner frequency

at 100 Hz and the wideband noise to be below 120 nV/√

Hz.

Figure 13 shows the reference noise voltage spectral density.

This figure shows the reference wideband noise to be below

125 nV/√

Hz.

1000

11M

100

10 100k10k1k100 10M

FREQUENCY – Hz

NOISE VOLTAGE – nV/ Hz

Figure 12. DAC Output Noise Voltage Spectral Density

1000

100

10 100k

10k1k100

10M

FREQUENCY – Hz

NOISE VOLTAGE – nV/ Hz

Figure 13. Reference Noise Voltage Spectral Density

BOARD LAYOUT

Designing with high resolution data converters requires careful

attention to board layout. Trace impedance is the first issue. A

306 µA current through a 0.5 Ω trace will develop a voltage

drop of 153 µV, which is 1 LSB at the 16-bit level for a 10 V

full-scale span. In addition to ground drops, inductive and ca-

pacitive coupling need to be considered, especially when high

accuracy analog signals share the same board with digital sig-

nals. Finally, power supplies need to be decoupled in order to

filter out ac noise.

Analog and digital signals should not share a common path.

Each signal should have an appropriate analog or digital return

routed close to it. Using this approach, signal loops enclose a

small area, minimizing the inductive coupling of noise. Wide PC

tracks, large gauge wire, and ground planes are highly recom-

mended to provide low impedance signal paths. Separate analog

and digital ground planes should also be utilized, with a single

interconnection point to minimize ground loops. Analog signals

should be routed as far as possible from digital signals and

should cross them at right angles.

One feature that the AD669 incorporates to help the user layout

is the analog pins (V

, V

, REF OUT, REF IN, SPAN/BIP

OFFSET, V

OUT

and AGND) are adjacent to help isolate analog

signals from digital signals.

SUPPLY DECOUPLING

The AD669 power supplies should be well filtered, well regu-

lated, and free from high frequency noise. Switching power sup-

plies are not recommended due to their tendency to generate

spikes which can induce noise in the analog system.

Decoupling capacitors should be used in very close layout prox-

imity between all power supply pins and ground. A 10 µF tanta-

lum capacitor in parallel with a 0.1 µF ceramic capacitor

provides adequate decoupling. V

and V

should be bypassed

to analog ground, while V

should be decoupled to digital

ground.

An effort should be made to minimize the trace length between

the capacitor leads and the respective converter power supply

and common pins. The circuit layout should attempt to locate

the AD669, associated analog circuitry and interconnections as

far as possible from logic circuitry. A solid analog ground plane

around the AD669 will isolate large switching ground currents.

For these reasons, the use of wire wrap circuit construction

is not recommended; careful printed circuit construction is

preferred.

GROUNDING

The AD669 has two pins, designated analog ground (AGND)

and digital ground (DGND.) The analog ground pin is the

“high quality” ground reference point for the device. Any exter-

nal loads on the output of the AD669 should be returned to

analog ground. If an external reference is used, this should also

be returned to the analog ground.

If a single AD669 is used with separate analog and digital

ground planes, connect the analog ground plane to AGND and

the digital ground plane to DGND keeping lead lengths as short

as possible. Then connect AGND and DGND together at the

AD669. If multiple AD669s are used or the AD669 shares ana-

log supplies with other components, connect the analog and

digital returns together once at the power supplies rather than at

each chip. This single interconnection of grounds prevents large

ground loops and consequently prevents digital currents from

flowing through the analog ground.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

AD669SQ

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Digital to Analog Converters - DAC IC MONO 16-BIT

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AD669SQ

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