AD669SQ Datasheet AD669BRZ, AD669ARZ, AD669BNZ | P7-P9

AD669

REV. A

–6–

If it is desired to adjust the gain and offset errors to zero, this

can be accomplished using the circuit shown in Figure 3b. The

adjustment procedure is as follows:

STEP1 . . . ZERO ADJUST

Turn all bits OFF and adjust zero trimmer, R4, until the output

reads 0.000000 volts (1 LSB = 153 µV).

STEP 2 . . . GAIN ADJUST

Turn all bits ON and adjust gain trimmer, R1, until the output

is 9.999847 volts. (Full scale is adjusted to 1 LSB less than the

nominal full scale of 10.000000 volts).

OUTPUT

GND

LDAC

DB15

(MSB)

(LSB)

DB0

16-BIT LATCH

10kV

AMP

AD669

10V REF

10kV

10.05kV

16-BIT LATCH

16-BIT DAC

50V

16kV

10kV

+15V

–15V

100V

–V

Figure 3b. 0 V to +10 V Unipolar Voltage Output with

Gain and Offset Adjustment

BIPOLAR CONFIGURATION

The circuit shown in Figure 4a will provide a bipolar output

voltage from –10.000000 V to +9.999694 V with positive full

scale occurring with all bits ON. As in the unipolar mode, resis-

tors R1 and R2 may be eliminated altogether to provide AD669

bipolar operation without any external components. Eliminating

these resistors will increase the gain error by 0.50% of FSR in

the bipolar mode.

50V

OUTPUT

GND

LDAC

DB15

(MSB)

(LSB)

DB0

16-BIT LATCH

10kV

AMP

AD669

10V REF

214

10kV

10.05kV

16-BIT LATCH

16-BIT DAC

50V

–V

Figure 4a.

10 V Bipolar Voltage Output

Gain offset and bipolar zero errors can be adjusted to zero using

the circuit shown in Figure 4b as follows:

STEP I . . . OFFSET ADJUST

Turn OFF all bits. Adjust trimmer R2 to give –10.000000 volts

output.

STEP II . . . GAIN ADJUST

Turn all bits ON and adjust R1 to give a reading of +9.999694

volts.

STEP III . . . BIPOLAR ZERO ADJUST

(Optional) In applications where an accurate zero output is re-

quired, set the MSB ON, all other bits OFF, and readjust R2

for zero volts output.

100V

OUTPUT

GND

LDAC

DB15

(MSB)

(LSB)

DB0

16-BIT LATCH

10kV

AMP

AD669

227

10V REF

10kV

10.05kV

16-BIT LATCH

16-BIT DAC

100V

–V

Figure 4b.

10 V Bipolar Voltage Output with Gain and

Offset Adjustment

It should be noted that using external resistors will introduce a

small temperature drift component beyond that inherent in the

AD669. The internal resistors are trimmed to ratio-match and

temperature-track other resistors on chip, even though their ab-

solute tolerances are ±20% and absolute temperature coeffi-

cients are approximately –50 ppm/°C. In the case that external

resistors are used, the temperature coefficient mismatch be-

tween internal and external resistors, multiplied by the sensitiv-

ity of the circuit to variations in the external resistor value, will

be the resultant additional temperature drift.

INTERNAL/EXTERNAL REFERENCE USE

The AD669 has an internal low noise buried Zener diode refer-

ence which is trimmed for absolute accuracy and temperature

coefficient. This reference is buffered and optimized for use in a

high speed DAC and will give long-term stability equal or supe-

rior to the best discrete Zener diode references. The perfor-

mance of the AD669 is specified with the internal reference

driving the DAC since all trimming and testing (especially for

gain and bipolar offset) is done in this configuration.

The internal reference has sufficient buffering to drive external

circuitry in addition to the reference currents required for the

DAC (typically 1 mA to REF IN and 1 mA to BIPOLAR OFF-

SET). A minimum of 2 mA is available for driving external

loads. The AD669 reference output should be buffered with an

external op amp if it is required to supply more than 4 mA total

current. The reference is tested and guaranteed to ±0.2% max

error. The temperature coefficient is comparable to that of the

gain TC for a particular grade.

If an external reference is used (10.000 V, for example), addi-

tional trim range should be provided, since the internal refer-

ence has a tolerance of ±20 mV, and the AD669 gain and

bipolar offset are both trimmed with the internal reference. The

optional gain and offset trim resistors in Figures 5 and 6 provide

enough adjustment range to null these errors.

It is also possible to use external references other than 10 volts

with slightly degraded linearity specifications. The recom-

mended range of reference voltages is +5 V to +10.24 V, which

AD669

REV. A

–7–

allows 5 V, 8.192 V and 10.24 V ranges to be used. For ex-

ample, by using the AD586 5 V reference, outputs of 0 V to

+5 V unipolar or ±5 V bipolar can be realized. Using the

AD586 voltage reference makes it possible to operate the

AD669 off of ±12 V supplies with 10% tolerances.

Figure 5 shows the AD669 using the AD586 5 V reference in

the bipolar configuration. This circuit includes two optional po-

tentiometers and one optional resistor that can be used to adjust

the gain, offset and bipolar zero errors in a manner similar to

that described in the BIPOLAR CONFIGURATION section.

Use –5.000000 V and +4.999847 as the output values.

50Ω

OUTPUT

GND

LDAC

DB15

(MSB)

(LSB)

DB0

–V

AD669

214

100Ω

10kΩ

AD586

REF IN

REF OUT

OUT

TRIM

GND

SPAN/BIP

OFFSET

Figure 5. Using the AD669 with the AD586 5 V Reference

USING THE AD669 WITH THE AD688 HIGH PRECISION

VOLTAGE REFERENCE

The AD669 is specified for gain drift from 15 ppm/°C to

25 ppm/°C (depending upon grade) using its internal 10 volt

reference. Since the internal reference contributes the vast ma-

jority of this drift, an external high precision voltage reference

will greatly improve performance over temperature. As shown in

Figure 6, the +10 volt output from the AD688 is used as the

AD669 reference. With a 3 ppm/°C drift over the industrial

temperature range, the AD688 will improve the gain drift by a

factor of 5 to a factor of 8 (depending upon the grade of the

AD669 being used). Using this combination may result in ap-

parent increases in initial gain error due to the differences

between the internal reference by which the device is laser

trimmed and the external reference with which the device is ac-

tually applied. The AD669 internal reference is specified to be

10 volts ±20 mV whereas the AD688 is specified as 10 volts

±5 mV. This may result in an additional 5 mV (33 LSBs) of ap-

parent initial gain error beyond the specified AD669 gain error.

The circuit shown in Figure 6 also makes use of the –10 V

AD688 output to allow the unipolar offset and gain to be ad-

justed to zero in the manner described in the UNIPOLAR

CONFIGURATION section.

100Ω

20k

100Ω

LDAC

DB15

(MSB)

(LSB)

DB0

-V

16-BIT LATCH

10k

AMP

AD669

10V REF

10k

10.05k

16-BIT LATCH

16-BIT DAC

10kΩ

10 8 12 11

AD688

GND

OUTPUT

0 TO +10V

–V

Figure 6. Using the AD669 with the AD688 High Precision

10 V Reference

AD669

REV. A

–8–

OUTPUT SETTLING AND GLITCH

The AD669’s output buffer amplifier typically settles to within

0.0008% FS (l/2 LSB) of its final value in 8 µs for a full-scale

step. Figures 7a and 7b show settling for a full-scale and an LSB

step, respectively, with a 2 kΩ, 1000 pF load applied. The guar-

anteed maximum settling time at +25°C for a full-scale step is

13 µs with this load. The typical settling time for a 1 LSB step is

2.5 µs.

The digital-to-analog glitch impulse is specified as 15 nV-s typi-

cal. Figure 7c shows the typical glitch impulse characteristic at

the code 011 . . . 111 to 100 . . . 000 transition when loading

the second rank register from the first rank register.

–10

+10

600

400

200

–200

–400

–600

VOLTS

µs

µV

a. –10 V to +10 V Full-Scale Step Settling

600

400

200

–200

–400

–600

µs

µV

234

b. LSB Step Settling

+10

–10

µs

234

c. D-to-A Glitch Impulse

Figure 7. Output Characteristics

DIGITAL CIRCUIT DETAILS

The bus interface logic of the AD669 consists of two indepen-

dently addressable registers in two ranks. The first rank consists

of a 16-bit register which is loaded directly from a 16-bit micro-

processor bus. Once the 16-bit data word has been loaded in the

first rank, it can be loaded into the 16-bit register of the second

rank. This double-buffered organization avoids the generation of

spurious analog output values.

The first rank latch is controlled by

CS and L1. Both of these

inputs are active low and are level-triggered. This means that

data present during the time when both

CS and L1 are low will

enter the latch. When either one of these signals returns high,

the data is latched.

The second rank latch is controlled by LDAC. This input is ac-

tive high and is also level-triggered. Data that is present when

LDAC is high will enter the latch, and hence the DAC will

change state. When this pin returns low, the data is latched in

the DAC.

Note that LDAC is not gated with

CS or any other control sig-

nal. This makes it possible to simultaneously update all of the

AD669’s present in a multi-DAC system by tying the LDAC

pins together. After the first rank register of each DAC has been

individually loaded and latched, the second rank registers are

then brought high together, updating all of the DACs at the

same time. To reduce bit skew, it is suggested to leave 100 ns

between the first rank load and the second rank load.

The first rank latch and second rank latch can be used together

in a master-slave or edge-triggered configuration. This mode of

operation occurs when LDAC and

CS are tied together with L1

tied to ground. Rising edges on the LDAC-

CS pair will update

the DAC with the data presented preceding the edge. The tim-

ing diagram for operation in this mode can be seen in Figure lb.

Note, however, that the sum of t

LOW

and t

HIGH

must be long

enough to allow the DAC output to settle to its new value.

Table I. AD669 Truth Table

CS L1 LDAC Operation

0 0 X First Rank Enable

X 1 X First Rank Latched

1 X X First Rank Latched

X X 1 Second Rank Enabled

X X 0 Second Rank Latched

0 0 1 All Latches Transparent

“X” = Don’t Care

It is possible to make the second rank register transparent by ty-

ing Pin 23 high. Any data appearing in the first rank register will

then appear at the output of the DAC. It should be noted, how-

ever, that the deskewing provided by the second rank latch is

then defeated, and glitch impulse may increase. If it is desired to

make both registers transparent, this can be done by tying Pins

5 and 6 low and Pin 23 high. Table I shows the truth table for

the AD669, while the timing diagram is found in Figure 1.

INPUT CODING

The AD669 uses positive-true binary input coding. Logic “1” is

represented by an input voltage greater than 2.0 V, and Logic

“0” is defined as an input voltage less than 0.8 V.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

AD669SQ

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Digital to Analog Converters - DAC IC MONO 16-BIT

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AD669SQ

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