AD669
REV. A
–3–
TIMING CHARACTERISTICS
V
CC
= +15 V, V
EE
= –15 V, V
LL
= +5 V, V
HI
= 2.4 V, V
LO
= 0.4 V
Limit Limit
Limit –408C to –558C to
Parameter +258C +858C +1258C Units
(Figure la)
t
CS
40 50 55 ns min
t
LI
40 50 55 ns min
t
DS
30 35 40 ns min
t
DH
10 10 15 ns min
t
LH
90 110 120 ns min
t
LW
40 45 45 ns min
(Figure lb)
t
LOW
130 150 165 ns min
t
HIGH
40 45 45 ns min
t
DS
120 140 150 ns min
t
DH
10 10 15 ns min
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical
test. Results from those tests are used to calculate outgoing quality levels. All
min and max specifications are guaranteed. Those shown in boldface are tested
on all production units.
AC PERFORMANCE CHARACTERISTICS
Parameter Limit Units Test Conditions/Comments
Output Settling Time 13 µs max 20 V Step, T
A
= +25°C
(Time to ±0.0008% FS 8 µs typ 20 V Step, T
A
= +25°C
with 2 k, 1000 pF Load) 10 µs typ 20 V Step, T
MIN
T
A
T
MAX
6 µs typ 10 V Step, T
A
= +25°C
8 µs typ 10 V Step, T
MIN
T
A
T
MAX
2.5 µs typ 1 LSB Step, T
MIN
T
A
T
MAX
Total Harmonic Distortion + Noise
A, B, S Grade 0.009 % max 0 dB, 1001 Hz; Sample Rate = 100 kHz; T
A
= +25°C
A, B, S Grade 0.07 % max –20 dB, 1001 Hz; Sample Rate = 100 kHz; T
A
= +25°C
A, B, S Grade 7.0 % max –60 dB, 1001 Hz; Sample Rate = 100 kHz; T
A
= +25°C
Signal-to-Noise Ratio 83 dB min T
A
= +25°C
Digital-to-Analog Glitch Impulse 15 nV-s typ DAC Alternately Loaded with 8000H and 7FFFH
Digital Feedthrough 2 nV-s typ DAC Alternately Loaded with 0000H and FFFFH; CS High
Output Noise Voltage 120 nV/
Hz typ Measured at V
OUT
, 20 V Span; Excludes Reference
Density (1 kHz – 1 MHz)
Reference Noise 125 nV/Hz typ Measured at REF OUT
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and
max specifications are guaranteed. Those shown in boldface are tested on all production units.
(With the exception of Total Harmonic Distortion + Noise and Signal-to-Noise
Ratio, these characteristics are included for design guidance only and are not subject to test. THD+N and SNR are 100% tested.
T
MIN
T
A
T
MAX
, V
CC
= +15 V, V
EE
= –15 V, V
LL
= +5 V except where noted.)
DATA
LDAC
t
DS
t
DH
CS
t
LW
t
LH
L1
t
CS
t
L1
Figure 1a. AD669 Level Triggered Timing Diagram
DATA
t
DS
t
DH
CS AND/OR
L1, LDAC
TIE CS AND/OR
L1 TO GROUND OR TOGETHER WITH LDAC
t
LOW
t
HIGH
Figure 1b. AD669 Edge Triggered Timing Diagram
AD669
REV. A
–4–
ORDERING GUIDE
Linearity Gain
Temperature Error Max TC max Package Package
Model Range T
MIN
–T
MAX
ppm/8C Description Option*
AD669AN –40°C to +85°C ±4 LSB 25 Plastic DIP N-28
AD669AR –40°C to +85°C ±4 LSB 25 SOIC R-28
AD669BN –40°C to +85°C ±2 LSB 15 Plastic DIP N-28
AD669BR –40°C to +85°C ±2 LSB 15 SOIC R-28
AD669AQ –40°C to +85°C ±4 LSB 15 Cerdip Q-28
AD669BQ –40°C to +85°C ±2 LSB 15 Cerdip Q-28
AD669SQ –55°C to +125°C ±4 LSB 15 Cerdip Q-28
AD669/883B** –55°C to +125°C** ** ** **
**N = Plastic DIP; Q = Cerdip; R = SOIC.
**Refer to AD669/883B military data sheet.
ESD SENSITIVITY
The AD669 features input protection circuitry consisting of large transistors and polysilicon series
resistors to dissipate both high-energy discharges (Human Body Model) and fast, low-energy pulses
(Charged Device Model). Per Method 3015.2 of MIL-STD-883: C, the AD669 has been classified
as a Class 2 device.
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test
equipment and discharge without detection. Unused devices must be stored in conductive foam or
shunts, and the foam should be discharged to the destination socket before devices are removed.
For further information on ESD precautions, refer to Analog Devices’ ESD Prevention Manual.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
*
V
CC
to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17.0 V
V
EE
to AGND . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17.0 V
V
LL
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 V
Digital Inputs (Pins 5 through 23) to DGND . . . . . . –1.0 V to
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0 V
REF IN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10.5 V
Span/Bipolar Offset to AGND . . . . . . . . . . . . . . . . . . . ±10.5 V
REF OUT, V
OUT
. . . . . . Indefinite Short To AGND, DGND,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
CC
, V
EE
, and V
LL
Power Dissipation (Any Package)
To +60°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
Derates above +60°C . . . . . . . . . . . . . . . . . . . . . .8.7 mW/°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PIN CONFIGURATION
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DGND
V
EE
V
CC
V
LL
CS
L1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TOP VIEW
(Not to Scale)
DB7
DB6
DB5
DB4
DB3
DB2
AGND
LDAC
DB0
DB1
AD669
REF OUT
REF IN
V
OUT
SPAN/BIP
OFFSET
THD + N – %
TEMPERATURE – °C
10
0.001
125
0.01
–25
–50
0.1
1
10075
50250
–60dB
–20dB
0dB
THD+N vs. Temperature
FREQUENCY – Hz
THD + N – %
10
0.001
0.01
0.1
1
100 100001000
–60dB
–20dB
0dB
THD+N vs. Frequency
AD669
REV. A
–5–
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY: Analog Devices defines inte-
gral nonlinearity as the maximum deviation of the actual, ad-
justed DAC output from the ideal analog output (a straight line
drawn from 0 to FS–1 LSB) for any bit combination. This is
also referred to as relative accuracy.
DIFFERENTIAL NONLINEARITY: Differential nonlinearity
is the measure of the change in the analog output, normalized to
full scale, associated with a 1 LSB change in the digital input
code. Monotonic behavior requires that the differential linearity
error be within ±1 LSB over the temperature range of interest.
MONOTONICITY: A DAC is monotonic if the output either
increases or remains constant for increasing digital inputs with
the result that the output will always be a single-valued function
of the input.
GAIN ERROR: Gain error is a measure of the output error be-
tween an ideal DAC and the actual device output with all 1s
loaded after offset error has been adjusted out.
OFFSET ERROR: Offset error is a combination of the offset
errors of the voltage-mode DAC and the output amplifier and is
measured with all 0s loaded in the DAC.
BIPOLAR ZERO ERROR: When the AD669 is connected for
bipolar output and 10 . . . 000 is loaded in the DAC, the devia-
tion of the analog output from the ideal midscale value of 0 V is
called the bipolar zero error.
DRIFT: Drift is the change in a parameter (such as gain, offset
and bipolar zero) over a specified temperature range. The drift
temperature coefficient, specified in ppm/°C, is calculated by
measuring the parameter at T
MIN
, 25°C and T
MAX
and dividing
the change in the parameter by the corresponding temperature
change.
TOTAL HARMONIC DISTORTION + NOISE: Total har-
monic distortion + noise (THD+N) is defined as the ratio of the
square root of the sum of the squares of the values of the har-
monics and noise to the value of the fundamental input fre-
quency. It is usually expressed in percent (%).
THD+N is a measure of the magnitude and distribution of lin-
earity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depend-
ing upon the amplitude of the output signal. Therefore, to be
the most useful, THD+N should be specified for both large and
small signal amplitudes.
SIGNAL-TO-NOISE RATIO: The signal-to-noise ratio is de-
fined as the ratio of the amplitude of the output when a full-
scale signal is present to the output with no signal present. This
is measured in dB.
DIGITAL-TO-ANALOG GLITCH IMPULSE: This is the
amount of charge injected from the digital inputs to the analog
output when the inputs change state. This is measured at half
scale when the DAC switches around the MSB and as many
as possible switches change state, i.e., from 011 . . . 111 to
100 . . . 000.
DIGITAL FEEDTHROUGH: When the DAC is not selected
(i.e.,
CS is held high), high frequency logic activity on the digi-
tal inputs is capacitively coupled through the device to show up
as noise on the V
OUT
pin. This noise is digital feedthrough.
THEORY OF OPERATION
The AD669 uses an array of bipolar current sources with MOS
current steering switches to develop a current proportional to
the applied digital word, ranging from 0 mA to 2 mA. A seg-
mented architecture is used, where the most significant four
data bits are thermometer decoded to drive 15 equal current
sources. The lesser bits are scaled using a R-2R ladder, then ap-
plied together with the segmented sources to the summing node
of the output amplifier. The internal span/bipolar offset resistor
can be connected to the DAC output to provide a 0 V to +10 V
span, or it can be connected to the reference input to provide a
–10 V to +10 V span.
SPAN/
BIP OFF
AGND
DGND
REF IN
REF OUT
V
OUT
LDAC
DB15
(MSB)
(LSB)
DB0
CS
L1
–V
EE
+V
CC
+V
LL
16-BIT LATCH
10k
AMP
AD669
22
7
6
5
23
27
28
10V REF
2143
26
24
10k
10.05k
16-BIT LATCH
16-BIT DAC
25
Figure 2. AD669 Functional Block Diagram
ANALOG CIRCUIT CONNECTIONS
Internal scaling resistors provided in the AD669 may be con-
nected to produce a unipolar output range of 0 V to +10 V or a
bipolar output range of –10 V to +10 V. Gain and offset drift
are minimized in the AD669 because of the thermal tracking of
the scaling resistors with other device components.
UNIPOLAR CONFIGURATION
The configuration shown in Figure 3a will provide a unipolar
0 V to +10 V output range. In this mode, 50 resistors are tied
between the span/bipolar offset terminal (Pin 26) and V
OUT
(Pin
25), and between REF OUT (Pin 28) and REF IN (Pin 27). It
is possible to use the AD669 without any external components
by tying Pin 28 directly to Pin 27 and Pin 26 directly to Pin 25.
Eliminating these resistors will increase the gain error by 0.25%
of FSR.
Figure 3a. 0 V to +10 V Unipolar Voltage Output

AD669SQ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC IC MONO 16-BIT
Lifecycle:
New from this manufacturer.
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