MPC9865
Rev 2, May/2006
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Advance Information
Clock Generator for PowerQUICC III
The MPC9865 is a PLL based clock generator specifically designed for
Freescale Microprocessor and Microcontroller applications including the
PowerPC and PowerQUICC. This device generates a microprocessor input
clock. The microprocessor clock is selectable in output frequency to any of the
commonly used microprocessor input and bus frequencies. The device offers
eight low skew clock outputs in two banks, each configurable to support different
clock frequencies. The extended temperature range of the MPC9865 supports
telecommunication and networking requirements.
Features
8 LVCMOS outputs for processor and other circuitry
Crystal oscillator or external reference input
25 or 33 MHz Input reference frequency
Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66,
50, 33, or 16 MHz
Buffered reference clock output (2 copies)
Low cycle-to-cycle and period jitter
100-lead PBGA package
100-lead Pb-free package available
3.3 V supply with 3.3 V or 2.5 V LVCMOS output supplies
Supports computing, networking, telecommunications applications
Ambient temperature range –40°C to +85°C
Functional Description
The MPC9865 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency
is selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers,
divide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60, or 120 to produce output frequencies of 200, 166, 133, 125, 111,
100, 83, 66, 50, 33, or 16 MHz. The single-ended LVCMOS outputs provide 8 low skew outputs for use in driving a microprocessor
or microcontroller clock input as well as other system components. The input reference, either crystal or external input is also
buffered to a separate dual outputs that my be used as the clock source for a Ethernet PHY if desired.
The reference clock may be provided by either an external clock input of 25 or 33 MHz. An internal oscillator requiring a
25 MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and
selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal
oscillator or external clock input is selected via the input pin of XTAL_SEL. Other than the crystal, no external components are
required for crystal oscillator operation. The REF_33 MHz configuration pin is used to select between a 33 and 25 MHz input
frequency.
The MPC9865 is packaged in a 100 lead MAPBGA package to optimize both performance and board density.
MPC9865
MICROPROCESSOR
CLOCK GENERATOR
SCALE 2 1
VF SUFFIX
VM SUFFIX (PB-FREE)
100 MAPBGA PACKAGE
CASE 1462-01
DATA SHEET
MPC9865
IDT™ Clock Generator for PowerQUICC III
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9865
1
Clock Generator for PowerQUICC III
Advanced Clock Drivers Devices
2 Freescale Semiconductor
MPC9865
Figure 1. MPC9865 Logic Diagram
Ref
1
0
PLL
2000 MHz
PLL_BYPASS
CLK_SEL
QA0
QA1
÷N
QA2
QA3
QB0
QB1
QB2
QB3
1
PCLK
0
CLK
MR
XTAL_IN
OSC
1
XTAL_OUT
REF_OUT0
XTAL_SEL
CLK_A[0:5]
CLK_B[0:5]
0
REF_33 MHz
PCLK
REF_OUT1
÷N
REF_OUT1_E
MPC9865
Clock Generator for PowerQUICC III NETCOM
IDT™ Clock Generator for PowerQUICC III
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9865
2
Advanced Clock Drivers Devices
Freescale Semiconductor 3
MPC9865
Table 1. Pin Configurations
Pin I/O Type Function Supply Active/State
CLK Input LVCMOS PLL Reference Clock Input (pull-down) V
DD
PCLK, PCLK Input LVPECL PLL reference clock input
(PCLK — pull-down, PCLK
— pull-up and pull-down)
V
DD
QA0, QA1,
QA2, QA3
QB0, QB1,
QB2, QB3
Output LVCMOS Clock Outputs V
DDOA
REF_OUT0
REF_OUT1
Output LVCMOS Reference Output (25 MHz or 33 MHz) V
DD
XTAL_IN Input LVCMOS Crystal Oscillator Input Pin V
DD
XTAL_OUT Output LVCMOS Crystal Oscillator Output Pin V
DD
CLK_SEL Input LVCMOS Select between CLK and PCLK input (pull-down) V
DD
High
XTAL_SEL Input LVCMOS Select between External Input and Crystal Oscillator Input
(pull-down)
V
DD
High
REF_33 MHz Input LVCMOS Selects 33 MHz input (pull-down) V
DD
High
REF_OUT1_E Input LVCMOS Enables REF_OUT1 output (pull-down) V
DD
High
MR
Input LVCMOS Master Reset (pull-up) V
DD
Low
PLL_BYPASS Input LVCMOS Select PLL or static test mode (pull-down) V
DD
High
CLK_A[0:5]
(1)
1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb).
Input LVCMOS Configures Bank A clock output frequency (pull-up) V
DD
CLK_B[0:5]
(2)
2. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb).
Input LVCMOS Configures Bank B clock output frequency (pull-up) V
DD
V
DD
3.3 V Supply
V
DDA
Analog Supply
V
DDOA
Output Supply — Bank A
V
DDOB
Output Supply — Bank B
GND Ground
Table 2. Function Table
Control Default 0 1
CLK_SEL 0 CLK PCLK
XTAL_SEL 0 CLKx XTAL
PLL_BYPASS 0 Normal Bypass
REF_OUT1_E 0 Disables REF_OUT1 Enables REF_OUT1
REF_33 MHz 0 Selects 25 MHz Reference Selects 33 MHz Reference
MR
1 Reset Normal
CLK_A and CLK_B control output frequencies. See Table 3 for specific device configuration.
MPC9865
Clock Generator for PowerQUICC III NETCOM
IDT™ Clock Generator for PowerQUICC III
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9865
3

MPC9865VM

Mfr. #:
Manufacturer:
Description:
Clock Generators & Support Products 8 LVCMOS OUT CLOCK GEN
Lifecycle:
New from this manufacturer.
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