Advanced Clock Drivers Devices
Freescale Semiconductor 5
MPC9865
OPERATION INFORMATION
Output Frequency Configuration
The MPC9865 was designed to provide the commonly
used frequencies in PowerQUICC, PowerPC and other
microprocessor systems. Table 3 lists the configuration
values that will generate those common frequencies. The
MPC9865 can generate numerous other frequencies that
may be useful in specific applications. The output frequency
(f
out
) of either Bank A or Bank B may be calculated by the
following equation.
f
out
= 2000 / N
where f
out
is in MHz and N = 2 * CLK_x[0:5]
This calculation is valid for all values of N from 8 to 126.
Note that N = 15 is a modified case of the configuration inputs
CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to
00111 or 7.
Crystal Input Operation
TBD
Power-Up and MR Operation
Figure 2 defines the release time and the minimum pulse
length for MR
pin. The MR release time is based upon the
power supply being stable and within V
DD
specifications. See
Table 9 for actual parameter values. The MPC9865 may be
configured after release of reset and the outputs will be stable
for use after lock indication is obtained.
Figure 2. MR Operation
Power Supply Bypassing
The MPC9865 is a mixed analog/digital product. The
architecture of the MPC9865 supports low noise signal
operation at high frequencies. In order to maintain its superior
signal quality, all V
DD
pins should be bypassed by
high-frequency ceramic capacitors connected to GND. If the
spectral frequencies of the internally generated switching
noise on the supply pins cross the series resonant point of an
individual bypass capacitor, its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the noise bandwidth.
Figure 3. V
CC
Power Supply Bypass
Power Consumption Calculation
For unloaded outputs the power consumption of the
MPC9855 can be calculated as follows.
P = V
DD
* I
DDBASE
+ n
A
* (V
DDOA
** 2 * C
PD
* f
A
)
+ n
B
* (V
DDOB
** 2 * C
PD
* f
B
)
where
V
DD
= core supply voltage
I
DDBASE
= base supply current
n
A
= number of A bank outputs (= 4)
n
B
= number of B bank outputs (= 4)
V
DDOA
= voltage supply on bank A outputs
V
DDOB
= voltage supply on bank B outputs
C
PD
= power dissipation capacitance
f
A
= frequency of bank A outputs
f
B
= frequency of bank B outputs
MR
V
DD
t
reset_rel
t
reset_pulse
V
DD
MPC9865
0.1 μF22 μF
0.1 μF
15 Ω
V
DD
V
DDA
