Advanced Clock Drivers Devices
8 Freescale Semiconductor
MPC9865
Figure 4. MPC9865 AC Test Reference (LVCMOS Outputs)
Table 9. AC Characteristics (V
DD
= 3.3 V ± 5%, V
DDOAB
= 3.3 V ± 5%, T
A
= –40°C to +85°C)
(1)
(2)
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50Ω to V
TT
.
Symbol Characteristics Min Typ Max Unit Condition
Input and Output Timing Specification
f
ref
Input Reference Frequency (25 MHz input)
Input Reference Frequency (33 MHz input)
XTAL Input
Input Reference Frequency in PLL Bypass Mode
(3)
3. In bypass mode, the MPC9865 divides the input reference clock.
25
33
25
250
MHz
MHz
MHz
MHz PLL bypass
f
VCO
VCO Frequency Range
2000 MHz
f
MCX
Output Frequency Bank A output
Bank B output
15.87
15.87
200
200
MHz
MHz
PLL locked
f
refPW
Reference Input Pulse Width 2 ns
f
refCcc
Input Frequency Accuracy 100 ppm
t
r
, t
f
Output Rise/Fall Time 150 500 ps 20% to 80%
DC Output Duty Cycle 45 50 55 % Bank A and B
PLL Specifications
t
LOCK
Maximum PLL Lock Time 10 ms
t
reset_ref
MR Hold Time on Power Up 10 ns
t
reset_pulse
MR Hold Time 10 ns
Skew and Jitter Specifications
t
sk(O)
Output-to-Output Skew (within a bank) 50 ps
t
sk(O)
Output-to-Output Skew (across banks A and B) 100 ps V
DDOA
= 3.3 V
V
DDOB
= 3.3 V
t
JIT(CC)
Cycle-to-Cycle Jitter 150 ps Bank A and B
t
JIT(PER)
Period Jitter 150 ps Bank A and B
t
r
, t
f
Output Rise/Fall Time TBD ns 20% to 80%
Pulse
Generator
Z = 50Ω
R
T
= 50Ω
Z
O
= 50Ω
DUT MPC9865
V
TT
Z
O
= 50Ω
R
T
= 50Ω
V
TT
