KAF−1001
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10
AC Operating Conditions
Table 9. CLOCK LEVELS
Description Symbol Level Minimum Nominal Maximum Units Pin Impedance
Vertical CCD Clock − Phase 1
fV1
Low −10.25 −10.0 −9.8 V
200 nF, 10 MW
Vertical CCD Clock − Phase 1
fV1
High 0.0 0.0 1.0 V
Vertical CCD Clock − Phase 2
fV2
Low −10.25 −10.0 −9.8 V
200 nF, 10 MW
Vertical CCD Clock − Phase 2
fV2
High 0.0 0.0 1.0 V
C
f
V1−V2
= 100 nF
Horizontal CCD Clock − Phase 1
fH1
Low −2.2 −2.0 −1.8 V
400 pF, 10 MW
Horizontal CCD Clock − Phase 1
fH1
High 7.8 8.0 8.2 V
Horizontal CCD Clock − Phase 2
fH2
Low −2.2 −2.0 −1.8 V
250 pF, 10 MW
Horizontal CCD Clock − Phase 2
fH2
High 7.8 8.0 8.2 V
C
f
H1−H2
= 200 nF
Reset Clock
fR
Low 2.0 3.0 3.5 V
10 pF, 10 MW
Reset Clock
fR
High 9.5 10.0 11.0 V
Description Symbo
l
Level
Using the High Gain
Output (V
OUT2
)
Using the High Dynamic
Range Output (V
OUT1
)
Units
Pin
Impedance
Min. Nom. Max. Min. Nom. Max.
Horizontal Clock − Phase 1
fH21
Low −4
fH2 Low fH2 Low
fH2
V
10 pF, 10 MW
Horizontal Clock − Phase 1
fH21
High −4
fH2 Low fH2 Low
fH2
V
Horizontal Clock − Phase 2
fH22
Low
fH2
fH2 Low fH2 Low
V
10 pF, 10 MW
Horizontal Clock − Phase 2
fH22
High
fH2
fH2 Low fH2 Low
V
1. When using V
OUT1
, fH21 is clocked identically with fH2 while fH22 is held at a static level. When using V
OUT2
, fH21 and fH22 are
exchanged so that fH22 is identical to fH2 and fH21 is held at a static level. The static level should be the same voltage as fH2 low.
2. The AC and DC operating levels are for room temperature operation. Operation at other temperatures may require adjustments of these
voltages. Pins shown with impedances greater than 1 MW are expected resistances. These pins are only verified to 1 MW.
3. fV1, 2 capacitances are accumulated gate oxide capacitance, and are an over-estimate of the capacitance.
4. This device is suitable for a wide range of applications requiring a variety of different operating conditions. Consult ON Semiconductor in
those situations in which operating conditions meet or exceed minimum or maximum levels.
KAF−1001
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11
TIMING
Table 10. REQUIREMENTS AND CHARACTERISTICS
Description Symbol Minimum Nominal Maximum Units Notes
fH1, fH2 Clock Frequency
f
H
4 5 MHz 1, 2, 3
fV1, fV2 Clock Frequency
f
V
100 125 kHz 1, 2, 3
Pixel Period (1 Count) t
PIX
200 250 ns
fH1, fH2 Setup Time t
f
HS
500 1,000 ns
fV1, fV2 Clock Pulse Width t
f
V
4 5
ms
2
Reset Clock Pulse Width
t
f
R
20 60 ns 4
Readout Time t
READOUT
226 286 ms 5
Integration Time t
INT
6
Line Time t
LINE
219 277
ms
7
1. 50% duty cycle values.
2. CTE may degrade above the nominal frequency.
3. Rise and fall times (10/90% levels) should be limited to 5−10% of clock period. Crossover of register clocks should be between 40−60% of
amplitude.
4. fR should be clocked continuously.
5. t
READOUT
= (1032 * t
LINE
)
6. Integration time (t
INT
) is user specified. Longer integration times will degrade noise performance due to dark signal fixed pattern and shot
noise.
7. t
LINE
= (3 * t
f
V
) + t
f
HS
+ (1044* t
PIX
) + t
PIX
KAF−1001
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12
Normal Readout
Figure 8. Timing Diagram
Photoactive
Line Timing Detail Pixel Timing Detail
Line Content
Dark Reference
Dummy Pixels
1−4 5−8 9−1032 1033−1042 1043−1044
V
SAT
Saturated pixel video output signal
V
DARK
Video output signal in no-light situation,
not zero due to J
DARK
V
PIX
Pixel video output signal level,
more electrons = more negative
V
ODC
Video level offset with respect to V
SUB
*
V
SUB
Analog ground
* See Image Acquisition section.
fV1
fV2
fH1
fH2
fR
1 Line
t
f
V
t
f
HS
t
PIX
1044 Counts
t
f
V
fH1
fH2
fR
V
OUT
t
f
R
t
PIX
V
SAT
V
DARK
V
ODC
V
SUB
V
PIX
1 Count
Frame Timing Detail
t
READOUT
t
INT
1 Frame = 1032 Lines
1032103121Line
fV1
fV2
fH1
fH2
NOTE: This device is suitable for a wide range of applications requiring a variety of different timing frequencies. Therefore, only maximum and
minimum values are shown above. Consult ON Semiconductor in those situations that require special consideration.

KAF-1001-AAA-CB-B2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Image Sensors FULL FRAME CCD IMAGE SENSOR
Lifecycle:
New from this manufacturer.
Delivery:
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