KAF−1001
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10
AC Operating Conditions
Table 9. CLOCK LEVELS
Description Symbol Level Minimum Nominal Maximum Units Pin Impedance
Vertical CCD Clock − Phase 1
fV1
Low −10.25 −10.0 −9.8 V
200 nF, 10 MW
Vertical CCD Clock − Phase 1
fV1
High 0.0 0.0 1.0 V
Vertical CCD Clock − Phase 2
fV2
Low −10.25 −10.0 −9.8 V
200 nF, 10 MW
Vertical CCD Clock − Phase 2
fV2
High 0.0 0.0 1.0 V
C
f
V1−V2
= 100 nF
Horizontal CCD Clock − Phase 1
fH1
Low −2.2 −2.0 −1.8 V
400 pF, 10 MW
Horizontal CCD Clock − Phase 1
fH1
High 7.8 8.0 8.2 V
Horizontal CCD Clock − Phase 2
fH2
Low −2.2 −2.0 −1.8 V
250 pF, 10 MW
Horizontal CCD Clock − Phase 2
fH2
High 7.8 8.0 8.2 V
C
f
H1−H2
= 200 nF
Reset Clock
fR
Low 2.0 3.0 3.5 V
10 pF, 10 MW
Reset Clock
fR
High 9.5 10.0 11.0 V
Description Symbo
Level
Using the High Gain
Output (V
OUT2
)
Using the High Dynamic
Range Output (V
OUT1
)
Units
Pin
Impedance
Min. Nom. Max. Min. Nom. Max.
Horizontal Clock − Phase 1
fH21
Low −4
fH2 Low fH2 Low
−
fH2
− V
10 pF, 10 MW
Horizontal Clock − Phase 1
fH21
High −4
fH2 Low fH2 Low
−
fH2
− V
Horizontal Clock − Phase 2
fH22
Low −
fH2
− −
fH2 Low fH2 Low
V
10 pF, 10 MW
Horizontal Clock − Phase 2
fH22
High −
fH2
− −
fH2 Low fH2 Low
V
1. When using V
OUT1
, fH21 is clocked identically with fH2 while fH22 is held at a static level. When using V
OUT2
, fH21 and fH22 are
exchanged so that fH22 is identical to fH2 and fH21 is held at a static level. The static level should be the same voltage as fH2 low.
2. The AC and DC operating levels are for room temperature operation. Operation at other temperatures may require adjustments of these
voltages. Pins shown with impedances greater than 1 MW are expected resistances. These pins are only verified to 1 MW.
3. fV1, 2 capacitances are accumulated gate oxide capacitance, and are an over-estimate of the capacitance.
4. This device is suitable for a wide range of applications requiring a variety of different operating conditions. Consult ON Semiconductor in
those situations in which operating conditions meet or exceed minimum or maximum levels.