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KAF-1001-AAA-CB-B2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
KAF−1001
www.onsemi.com
4
Figure 3. Output Schematic
Source
Follower
#1
Source
Follower
#2
HCCD
Charge
Transfer
Floating
Diffusion
V
DD
V
OUT
V
RD
V
OG
R
H2
H1
H2
H1L
V
LG
Image Acquisition
An image is acquired when incident light, in the form of
photons, falls on the array of pixels in the vertical CCD
register and creates electron-hole pairs (or simply electrons)
within the silicon substrate. This charge is collected locally
by the formation of potential wells created at each pixel site
by induced voltages on the vertical register clock lines
(fV1, fV2). These same clock lines are used to implement
the transport mechanism as well. The amount of charge
collected at each pixel is linearly dependent on light level
and exposure time and non-linearly dependent on
wavelength until the potential well capacity is exceeded. At
this point charge will ‘bloom’ into vertically adjacent pixels.
Charge Transport
Integrated charge is transported to the output in a two-step
process. Rows of charge are first shifted line by line into the
horizontal CCD. ‘Lines’ of charge are then shifted to the
output pixel by pixel. Referring to the timing diagram,
integration of charge is performed with fV1 and fV2 held
low. Transfer to horizontal CCD begins when fV1 is
brought high causing charge from the fV1 and fV2 gates
to combine under the fV1 gate.
fV1 and fV2 now reverse their polarity causing the
charge packets to ‘spill’ forward under the fV2 gate of the
next pixel. The rising edge of fV2 also transfers the first line
of charge into the horizontal CCD. A second phase transition
places the charge packets under the fV1 electrode of the
next pixel. The sequence completes when fV1 is brought
low. Clocking of the vertical register in this way is known as
accumulation mode clocking. Next, the horizontal CCD
reads out the first line of charge using traditional
complementary clocking (using fH1 and fH2 pins) as
shown. The falling edge of fH2 forces a charge packet over
the output gate (OG) onto one of the output nodes (floating
diffusion) which controls the output amplifier. The cycle
repeats until all lines are read.
KAF−1001
www.onsemi.com
5
Physical Description
Pin Description and Device Orientation
Figure 4. Pinout Diagram
SUB 1
fV2 2
fV1 3
SUB 4
VOUT2 5
VDD2 6
VLG 7
VSS 8
fR9
VRD 10
VDD1 11
VOUT1 12
Pixel (1024, 1024)
25 fV2
14 fH21
15 fH22
16 fH1
17 fH2
18 N/C
19 N/C
20 N/C
21 fV2
22 fV1
23 GUARD
24 fV1
Pixel (1, 1)
VOG 13
26 SUB
Table 4. PIN DESCRIPTION
Pin Name Description
1 SUB Substrate
2
fV2
Vertical (Parallel) CCD Clock − Phase 2
3
fV1
Vertical (Parallel) CCD Clock − Phase 1
4 SUB Substrate
5 VOUT2 Video Output from High Sensitivity
Two-Stage Amplifier
6 VDD2 High Sensitivity Two-Stage Amplifier
Supply
7
VLG
First Stage Load Transistor Gate for
Two-Stage Amplifier
8 VSS Output Amplifier Return
9
fR
Reset Clock
10 VRD Reset Drain
11 VDD1 High Dynamic Range Single-Stage
Amplifier Supply
12 VOUT1 Video Output from High Dynamic Range
Single-Stage Amplifier
13 VOG Output Gate
Pin Name Description
14
fH21
Last Horizontal (Serial) CCD Phase − Split
Gate
15
fH22
Last Horizontal (Serial) CCD Phase − Split
Gate
16
fH1
Horizontal (Serial) CCD Clock − Phase 1
17
fH2
Horizontal (Serial) CCD Clock − Phase 2
18
N/C
No Connection
19
N/C
No Connection
20 N/C No Connection
21
fV2
Vertical (Parallel) CCD Clock − Phase 2
22
fV1
Vertical (Parallel) CCD Clock − Phase 1
23 GUARD Guard Ring
24
fV1
Vertical (Parallel) CCD Clock − Phase 1
25
fV2
Vertical (Parallel) CCD Clock − Phase 2
26 SUB Substrate
1. Pins 3, 22, and 24 must be connected together − only one
Phase 1 clock driver is required.
2. Pins 2, 21, and 25 must be connected together − only one
Phase 2 clock driver is required.
KAF−1001
www.onsemi.com
6
IMAGING PERFORMANCE
Typical Operational Conditions
All values derived using nominal operating conditions
with the recommended timing. Correlated doubling
sampling of the output is assumed and recommended. Many
units are expressed in electrons: to convert to voltage,
multiply by the amplifier sensitivity.
Specifications
Table 5. SPECIFICATIONS
Description Symbol Min. Nom. Max. Units Notes
Verification
Plan
ELECTRO-OPTICAL
Optical Fill Factor
FF − 100 − %
Photoresponse
Non-uniformity
PRNU − − 5 % rms Full Array Die
10
Quantum Efficiency
(450, 550, 650 nm)
QE − − − Design
11
CCD PARAMETERS COMMON TO BOTH OUTPUTS
Sat. Signal − V
CCD
Register Ne
−
SAT
450 500 − ke
−
2 Design
11
Dark Current J
D
−
−
15.3
550
30
1,080
pA/cm
2
e
−
/pix/sec
25°C
(Mean of All Pixels)
Die
10
Dark Current Doubling Temp DCDR 5 6 7 °C Design
11
Dark Signal Non-uniformity DSNU − − 1,080 e
−
/pix/sec 4 Die
10
Charge Transfer Efficiency CTE − 0.99997 − 5 Die
10
V-H CCD Transfer Time t
VH
− 32 −
ms
6, 7 Design
11
Blooming Suppression B
S
− None −
CCD PARAMETERS SPECIFIC TO HIGH OUTPUT AMPLIFIER
Output Sensitivity
V
OUT
/Ne
−
9 11 −
mV/e
−
Design
11
Sat. Signal Ne
−
SAT
180 200 240 ke
−
1 Design
11
Total Sensor Noise ne
−
TOTAL
− 13 20 e
−
rms 8 Design
11
Horizontal CCD Frequency f
H
− 2 5 MHz 6 Design
11
Dynamic Range DR 79 83 − dB 9 Design
11
CCD PARAMETERS SPECIFIC TO LOW GAIN (HIGH DYNAMIC RANGE) OUTPUT AMPLIFIER
Output Sensitivity
V
OUT
/Ne
−
1.7 2
mV/e
−
Die
10
Sat. Signal Ne
−
SAT
1,400 1,500 1,800 ke
−
3 Design
11
Total Sensor Noise ne
−
TOTAL
− 22 30 e
−
rms 8 Die
10
Horizontal CCD Frequency f
H
− 0.5 2 MHz 6 Design
11
Dynamic Range DR 93 97 − dB 9 Design
11
1. Point where the output saturates when operated with nominal voltages.
2. Signal level at the onset of blooming in the vertical (parallel) CCD register.
3. Maximum signal level at the output of the high dynamic range output. This signal level will only be achieved when binning pixels containing
large signals.
4. None of 64 sub arrays (128 × 128) exceed the maximum dark current specification.
5. For 2 MHz data rate and T = 30°C to −40°C.
6. Using maximum CCD frequency and/or minimum CCD transfer times may compromise performance.
7. Time between the rising edge of fV1 and the first falling edge of fH1.
8. At T
INTEGRATION
= 0; data rate = 1 MHz; temperature = −30°C.
9. Uses 20LOG (Ne
−
SAT
/ ne
−
TOTAL
) where Ne
−
SAT
refers to the amplifier saturation signal.
10.A parameter that is measured on every sensor during production testing.
11. A parameter that is quantified during the design verification activity.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

KAF-1001-AAA-CB-B2

Mfr. #:
Buy KAF-1001-AAA-CB-B2
Manufacturer:
ON Semiconductor
Description:
Image Sensors FULL FRAME CCD IMAGE SENSOR
Lifecycle:
New from this manufacturer.
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