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ZL40200LDG1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
VDD_driver
VDD_driver
VDD
ZL40200
clk_p
clk_n
CMOS
Driver
R
R
C
Vref = VDD_driver/2
R=10 k ohm, C = 100 nF
Figure 10 - CMOS Input DC Coupled Referenced to VDD/2
VDD
VDD_driver
VDD
ZL40200
clk_p
clk_n
CMOS
Driver
R2
C
RA
R3
R1
Figure 11 - CMOS Input DC Coupled Referenced to Ground
Table 1 - Component Values for Single Ended Input Reference to Ground
VDD_driver R1 (kΩ) R2 (kΩ) R3 (kΩ) RA (kΩ) C (pF)
1.5 1.25 3.075 open 10 10
1.8 1 3.8 open 10 10
2.5 0.33 4.2 open 10 10
3.3 0.75 open 4.2 10 10
ZL40200 Data Sheet
10
Microsemi Corporation
* For frequencies below 100 MHz, increase C to avoid signal integrity issues.
ZL40200 Data Sheet
11
Microsemi Corporation
3.2 Clock Outputs
LVPECL has a very low output impedance and a differential signal swing between 1V and 1.6 V. A simplified
diagram for the output stage is shown in Figure 12.The LVPECL to LVDS output termination is not shown since
there is a separate device that has the same input and LVDS outputs.
out_p
out_n
Figure 12 - Simplified Output Driver
The methods to terminate the ZL40200 LVPECL drivers are shown in the following figures.
LVPECL
Receiver
50
Ohms
50
Ohms
VDD
VDD_Rx
Z
o
= 50 Ohms
Z
o
= 50 Ohms
ZL40200
clk_p
clk_n
VDD - 2
Figure 13 - LVPECL Basic Output Termination
LVPECL
Receiver
50
Ohms
50
Ohms
VDD
VDD_Rx
Z
o
= 50 Ohms
Z
o
= 50 Ohms
ZL40200
clk_p
clk_n
R
For VDD = 2.5 V: R = 20 Ohms
For VDD = 3.3 V: R = 50 Ohms
Figure 14 - LVPECL Parallel Output Termination
ZL40200 Data Sheet
12
Microsemi Corporation
R2 R2
VDD
VDD_Rx
Z
o
= 50 Ohms
Z
o
= 50 Ohms
ZL40200
clk_p
clk_n
For VDD = 2.5 V: R1 = 250 Ohms, R2 = 62.5 Ohms
For VDD = 3.3 V: R1 = 127 Ohms, R2 = 82 Ohms
VDD
R1 R1
LVPECL
Receiver
Figure 15 - LVPECL Parallel Thevenin-Equivalent Output Termination
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

ZL40200LDG1

Mfr. #:
Buy ZL40200LDG1
Manufacturer:
Microchip / Microsemi
Description:
Clock Buffer 1:2 LVPECL Fanout Buffer w/Ext. Term.
Lifecycle:
New from this manufacturer.
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