ZL40200 Data Sheet
16
Microsemi Corporation
3.4 Power Supply
This device operates with either a 2.5V supply or 3.3V supply.
3.4.1 Sensitivity to power supply noise
Power supply noise from sources such as switching power supplies and high-power digital components such as
FPGAs can induce additive jitter on clock buffer outputs. The ZL40200 is equipped with a low drop out (LDO) power
regulator and on-chip bulk capacitors to minimize additive jitter due to power supply noise. The LDO regulator on
the ZL40200 allows this device to have superior performance even in the presence of external noise sources. The
on-chip regulation, recommended power supply filtering, and good PCB layout all work together to minimize the
additive jitter from power supply noise.
The performance of these clock buffers in the presence o
f power supply noise is detailed in ZLAN-403, “Power
Supply Rejection in Clock Buffers” which is available from Applications Engineering.
3.4.2 Power supply filtering
For optimal jitter performance, the device should be isolated from the power planes connected to its power supply
pins as shown in Figure 20.
• 10 µF capacitors should be size 0603 or size 080
5 X5R or X7R ceramic, 6.3 V minimum rating
• 0.1 µF capacitors should be
size 0402 X5R ceramic, 6.3 V minimum rating
• Capacitors should be placed next to the
connected device power pins
• a 0.3 ohm resistor is recommended for the filter shown in Figure 20
Figure 20 - Decoupling Connections for Power Pins
VDD
0.3 Ohms
0.1 µF
10 µF
ZL40200
8
13
3.4.3 PCB layout considerations
The power nets in Figure 20 can be implemented either as a plane island or routed power topology without
changing the overall jitter p
erformance of the device.
