MAX1401EAI+ Datasheet MAX1401EAI+, MAX1401CAI+, MAX1401EAI+T | P16-P18

MAX1401

+3V, 18-Bit, Low-Power, Multichannel,

Oversampling (Sigma-Delta) ADC

16 ______________________________________________________________________________________

FSYNC: (Default = 0) Filter Sync Bit. When FSYNC = 0,

conversions are automatically performed at a data rate

determined by CLK, FS1, FS0, MF1, and MF0 bits.

When FSYNC = 1, the digital filter and analog modulator

are held in reset, inhibiting normal self-timed operation.

This bit may be used to convert on command to mini-

mize the settling time to valid output data, or to synchro-

nize operation of a number of MAX1401s. FSYNC does

not reset the serial interface or the 0/DRDY flag. To clear

the 0/DRDY flag while FSYNC is active, simply read the

data register.

Global Setup Register 1

A1, A0: (Default = 0, 0) Channel-Selection Control Bits.

These bits (combined with the state of the DIFF, M1,

and M0 bits) determine the channel selected for con-

version according to Tables 8, 9, and 10. These bits

are ignored if the SCAN bit is set.

MF1, MF0: (Default = 0, 0) Modulator Frequency Bits.

MF1 and MF0 determine the ratio of CLKIN oscillator fre-

quency to modulator operating frequency. They affect

the output data rate, the position of the digital filter notch

frequencies, and the power dissipation of the device.

Achieve lowest power dissipation with MF1 = 0 and MF0

= 0. Highest power dissipation and fastest output data

rate occur with these bits set to 1, 1 (Table 2).

CLK: (Default = 1) CLK Bit. The CLK bit is used in con-

junction with X2CLK to tell the MAX1401 the frequency

of the CLKIN input signal. If CLK = 0, a CLKIN input fre-

quency of 1.024MHz (2.048MHz for X2CLK = 1) is

expected. If CLK = 1, a CLKIN input frequency of

2.4576MHz (4.9152MHz for X2CLK = 1) is expected.

This bit affects the decimation factor in the digital filter

and thus the output data rate (Table 2).

FS1, FS0: (Default = 0, 1) Filter Selection Bits. These

bits (in conjunction with the CLK bit) control the deci-

mation ratio of the digital filter. They determine the out-

put data rate, the position of the digital filter frequency

response notches, and the noise present in the output

result (Table 2).

FAST: (Default 0) Fast Bit. FAST = 0 causes the digital

filter to perform a SINC

filter function on the modulator

data stream. The output data rate will be determined by

the values in the CLK, FS1, FS0, MF1, and MF0 bits

(Table 2). The settling time for SINC

function is 3 · [1 /

(output data rate)]. In SINC

mode, the MAX1401 auto-

matically holds the DRDY signal false (after any signifi-

cant configuration change) until settled data is

available. FAST = 1 causes the digital filter to perform a

SINC

filter function on the modulator data stream. The

signal-to-noise ratio achieved with this filter function is

less than that of the SINC

filter; however, SINC

settles

in a single output sample period rather than a minimum

of three output sample periods for SINC

. When switch-

ing from SINC

to SINC

mode, the DRDY flag will be

deasserted and reasserted after the filter has fully set-

tled. This mode change requires a minimum of three

samples.

Global Setup Register 2

SCAN: (Default = 0) Scan Bit. Setting this bit to a 1

causes sequential scanning of the input channels as

determined by DIFF, M1, and M0 (see Scanning (SCAN

Mode) section). When SCAN = 0, the MAX1401 repeat-

edly measures the unique channel selected by A1, A0,

DIFF, M1, and M0 (Table 4).

M1, M0: (Default 0, 0) Mode Control Bits. These bits

control access to the calibration channels CALOFF and

CALGAIN. When SCAN = 0, setting M1 = 0 and M0 = 1

selects the CALOFF input, and M1 = 1 and M0 = 0

selects the CALGAIN input (Table 3). When SCAN = 1

and M1 ≠ M0, the scanning sequence includes both

CALOFF and CALGAIN inputs (Table 4). When SCAN is

set to 1 and the device is scanning the available input

First Bit (MSB) (LSB)

Global Setup Register 2

Global Setup Register 1

FUNCTION

FILTER SELECTION

FS0

FS1

Name FAST

MODULATOR

FREQUENCY

MF0

MF1

CHANNEL SELECTION

Defaults

CLKA1

FUNCTION

RESERVED

BOUT

Name X2CLK

MODE CONTROL

BUFF

0Defaults

DIFFSCAN

MAX1401

+3V, 18-Bit, Low-Power, Multichannel,

Oversampling (Sigma-Delta) ADC

______________________________________________________________________________________ 17

channels, selection of either calibration mode (01 or 10)

will cause the scanning sequence to be extended to

include a conversion on both the CALGAIN+/CALGAIN-

input pair and the CALOFF+/CALOFF- input pair. The

exact sequence depends on the state of the DIFF bit

(Table 4). When scanning, the calibration channels use

the PGA gain, format, and DAC settings defined by the

contents of Transfer Function Register 3.

BUFF: (Default = 0) The BUFF bit controls operation of

the input buffer amplifiers. When this bit is 0, the inter-

nal buffers are bypassed and powered down. When

this bit is set high, the buffers drive the input sampling

capacitors and minimize the dynamic input load.

DIFF: (Default = 0) Differential/Pseudo-Differential Bit.

When DIFF = 0, the part is in pseudo-differential mode,

and AIN1–AIN5 are measured respective to AIN6, the

analog common. When DIFF = 1, the part is in differen-

tial mode with the analog inputs defined as AIN1/AIN2,

AIN3/AIN4, and AIN5/AIN6. The available input chan-

nels for each mode are tabulated in Table 5. Note that

DIFF also affects the scanning sequence when the part

is placed in SCAN mode (Table 4).

BOUT: (Default = 0) Burn-out Current Bit. Setting BOUT

= 1 connects 100nA current sources to the selected

analog input channel. This mode is used to check that a

transducer has not burned out or opened circuit. The

burn-out current source must be turned off (BOUT = 0)

before measurement to ensure best linearity.

RESERVED: (Default = 0) Reserved Bit. A 0 must be

written to this location.

X2CLK: (Default = 0) Times-Two Clock Bit. Setting this

bit to 1 selects a divide-by-2 prescaler in the clock sig-

nal path. This allows use of a higher frequency crystal

or clock source and improves immunity to asymmetric

clock sources.

Table 2. Data Output Rate vs. CLK, Filter Select, and Modulator Frequency Bits

* Data rates offering noise-free 16-bit resolution.

Note: When FAST = 0, f

-3dB

= 0.262 · Data Rate. When FAST = 1, f

-3dB

= 0.443 · Data Rate.

Note: Default condition is in bold print.

Table 3. Special Modes Controlled by M1, M0 (SCAN = 0)

MF0

MF1

CLK

2400 4800400 4804.91522.4576

1200 2400200 2404.91522.4576

600 1200100 1204.91522.4576

300 60050

4.9152

2.4576

800 1600160 2002.0481.024

400 80080 1002.0481.024

200 40040 502.0481.024

FS1, FS0

(1, 0)

FS1, FS0

(1, 1)

FS1, FS0*

(0, 0)

100

AVAILABLE OUTPUT DATA RATES

(sps)

X2CLK = 0

200

FS1, FS0*

(0, 1)

20 25

X2CLK = 1

2.0481.024

Calibrate Offset: In this mode the MAX1401 converts the voltage applied across CALOFF+

and CALOFF-. The PGA gain, DAC, and format settings of the selected channel (defined by

DIFF, A1, A0) are used.

Reserved: Do not use.

Calibrate Gain: In this mode the MAX1401 converts the voltage applied across CALGAIN+

and CALGAIN-. The PGA gain, DAC, and format settings of the selected channel (defined by

DIFF, A1, A0) are used.

Normal Mode: The device operates normally.

M1 DESCRIPTION

CLKIN FREQUENCY,

CLKIN

(MHz)

MAX1401

+3V, 18-Bit, Low-Power, Multichannel,

Oversampling (Sigma-Delta) ADC

18 ______________________________________________________________________________________

Special Function Register (Write-Only)

MDOUT: (Default = 0) Modulator Out Bit. MDOUT = 0

enables data readout on the DOUT pin, the normal con-

dition for the serial interface. MDOUT = 1 changes the

function of the DOUT and INT pins, providing raw, sin-

gle-bit modulator output instead of the normal serial-

data interface output. This allows custom filtering

directly on the modulator output, without going through

the on-chip digital filter. The INT pin provides a clock to

indicate when the modulator data at DOUT should be

sampled (falling edge of INT). Note that in this mode,

the on-chip digital filter continues to operate normally.

When MDOUT is returned to 0, valid data may be

accessed through the normal serial-interface read

operation.

FULLPD: (Default = 0) Complete Power-Down Bit.

FULLPD = 1 forces the part into a complete power-

down condition, which includes the clock oscillator. The

serial interface continues to operate. The part requires a

hardware reset to recover correctly from this condition.

Note: Changing the reserved bits in the special-func-

tion register from the default status of all 0s will select

one of the reserved modes and the part will not operate

as expected. This register is a write-only register.

However, in the event that this register is mistakenly

read, clock 24 bits of data out of the part to restore it to

the normal interface-idle state.

Transfer-Function Registers

The three transfer-function registers control the method

used to map the input voltage to the output codes. All

of the registers have the same format. The mapping of

control registers to associated channels depends on

the mode of operation and is affected by the state of

M1, M0, DIFF, and SCAN (Tables 8, 9, and 10).

Table 4. SCAN Mode Scanning

Sequences (SCAN = 1)

Table 5. Available Input Channels

(SCAN = 0)

Note: All other combinations reserved.

Special Function Register (Write-Only)

Transfer-Function Register

0 1

AIN1–AIN6, AIN2–AIN6, AIN3–AIN6,

AIN4–AIN6, AIN5–AIN6, CALOFF,

CALGAIN

1 0

0 0 AIN1–AIN2, AIN3–AIN4, AIN5–AIN61

AIN1–AIN6, AIN2–AIN6, AIN3–AIN6,

AIN4–AIN6, AIN5–AIN6, CALOFF,

CALGAIN

AIN1–AIN6, AIN2–AIN6, AIN3–AIN6,

AIN4–AIN6, AIN5–AIN6

0 1

1 0

AIN1–AIN2, AIN3–AIN4, AIN5–AIN6,

CALOFF, CALGAIN

AIN1–AIN2, AIN3–AIN4, AIN5–AIN6,

CALOFF, CALGAIN

DIFF SEQUENCE

0 1 CALOFF0

1 0

0 0 AIN1–AIN2, AIN3–AIN4, AIN5–AIN61

CALGAIN

AIN1–AIN6, AIN2–AIN6, AIN3–AIN6,

AIN4–AIN6

0 1

1 0 CALGAIN1

CALOFF1

DIFF AVAILABLE CHANNELS

0 0

Defaults

RESERVED BITS

MDOUT

FULLPDName

RESERVED BITS

FUNCTION

First Bit (MSB) (LSB)

G2 D3

0 0Defaults

PGA GAIN CONTROL

D0Name

OFFSET CORRECTION

0 0

D1G0

00 0

FUNCTION

First Bit (MSB) (LSB)

U/B

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36

MAX1401EAI+

Mfr. #:

Buy MAX1401EAI+

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 18-Bit 5Ch 4.8ksps 1.25V Precision ADC

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

MAX1401EAI+

MAX1401EAI+

Products related to this Datasheet