MAX1401
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
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/* Assumptions:
** The MAX140X's CS pin is tied to ground
** The MAX140X's INT pin drives a falling-edge-triggered interrupt
** MAX140X's DIN is driven by MOSI, DOUT drives MISO, and SCLK drives SCLK
*/
/* Low-level function to write 8 bits using 68HC11 SPI */
void WriteByte (BYTE x)
{
/* System-dependent: write to SPI hardware and wait until it is finished */
HC11_SPDR = x;
while (HC11_SPSR & HC11_SPSR_SPIF) { /* idle loop */ }
}
/* Low-level function to read 8 bits using 68HC11 SPI */
BYTE ReadByte (void)
{
/* System-dependent: use SPI hardware to clock in 8 bits */
HC11_SPDR = 0xFF;
while (HC11_SPSR & HC11_SPSR_SPIF) { /* idle loop */ }
return HC11_SPDR;
}
/* Low-level interrupt handler called whenever the MAX140X's INT pin goes low.
** This function reads new data from the MAX140X and feeds it into a
** user-defined function Process_Data().
*/
void HandleDRDY (void)
{
BYTE data_H_bits, data_M_bits, data_L_bits; /* storage for data register */
WriteByte(0x78); /* read the latest data regsiter value */
data_H_bits = ReadByte();
data_M_bits = ReadByte();
data_L_bits = ReadByte();
Process_Data(data_H_bits, data_M_bits, data_L_bits);
/* System-dependent: re-enable the interrupt service routine */
}
/* High-level function to configure the MAX140X's registers
** Refer to data sheet for custom setup values.
*/
void Initialize (void)
{
/* System-dependent: configure the SPI hardware (CPOL=1,CPHA=1) */
/* write to all of configuration registers */
MY_GS1 = 0x0A; MY_GS2 = 0x00; MY_GS3 = 0x00;
MY_TF1 = 0x00; MY_TF2 = 0x00; MY_TF3 = 0x00;
WriteByte(0x10); WriteByte(MY_GS1); /* write Global Setup 1 */
WriteByte(0x20); WriteByte(MY_GS2); /* write Global Setup 2 */
WriteByte(0x30); WriteByte(MY_GS3); /* write Global Setup 3 */
WriteByte(0x40); WriteByte(MY_TF1); /* write Transfer Function 1 */
WriteByte(0x50); WriteByte(MY_TF2); /* write Transfer Function 2 */
WriteByte(0x60); WriteByte(MY_TF3); /* write Transfer Function 3 */
/* System-dependent: enable the data-ready (DRDY) interrupt handler */
}
Listing 1. Example SPI Interface
