Rev D 6/9/15 4 FEMTOCLOCKS CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
844002I-01 DATA SHEET
Table 3C. LVDS DC Characteristics, V
DD
= V
DDA
= V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Table 4. Crystal Characteristics
AC Electrical Characteristics
Table 5. AC Characteristics, V
DD
= V
DDA
= V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OD
Differential Output Voltage 240 550 mV
V
OD
V
OD
Magnitude Change 40 mV
V
OS
Offset Voltage 0.7 1.1 1.5 V
V
OS
V
OS
Magnitude Change 50 mV
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 22.4 25 27.2 MHz
Equivalent Series Resistance (ESR) 50
Shunt Capacitance 7pF
Drive Level 1mW
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency
FSEL[1:0] = 00 140 170 MHz
FSEL[1:0] = 01 112 136 MHz
FSEL[1:0] = 10 56 68 MHz
tsk(o) Output Skew; NOTE 1, 2 5 20 ps
tjit(Ø)
RMS Phase Jitter, (Random);
NOTE 3
156.25MHz, (1.875MHz – 20MHz) 0.41 ps
125MHz, (1.875MHz – 20MHz) 0.44 ps
62.5MHz, (1.875MHz – 20MHz) 0.47 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 250 550 ps
odc Output Duty Cycle 48 52 %
t
L
PLL Lock Time 100 ms
