FEMTOCLOCKS CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER 7 Rev D 6/9/15
844002I-01 DATA SHEET
Differential Offset Voltage Setup
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform-
ance, power supply isolation is required. The 844002I-01 provides
separate power supplies to isolate any high switching noise from
the outputs to the internal PLL. V
DD,
V
DDA
and V
DDO
should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic V
DD
pin and also shows that V
DDA
requires that an additional 10 resistor along with a 10F bypass
capacitor be connected to the V
DDA
pin.
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
REF_CLK Input
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1k resistor can be tied from the REF_CLK to
ground.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied
from XTAL_IN to ground.
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or
terminated with 100 across. If they are left floating, we
recommend that there is no trace attached.
V
DD
V
DDA
2.5V
10Ω
10µF.01µF
.01µF
