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74AUP1G97GXZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Nexperia
74AUP1G97
Low-power configurable multiple function gate
74AUP1G97 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 10 — 28 March 2017
19 / 25
References
Outline
version
European
projection
Issue date
IEC JEDEC JEITA
SOT1202
sot1202_po
10-04-02
10-04-06
Unit
mm
max
nom
min
0.35 0.04 1.05
1.00
0.95
1.05
1.00
0.95
0.55 0.35
0.40
0.35
0.32
A
(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON6: extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm
SOT1202
A
1
b
0.20
0.15
0.12
D E e e
1
L
0.35
0.30
0.27
L
1
0 0.5 1 mm
scale
terminal 1
index area
D
E
(4×)
(2)
e
1
e
1
e
L
b
1 2 3
L
1
6 5 4
(6×)
(2)
A
A
1
Figure 25. Package outline SOT1202 (XSON6)
Nexperia
74AUP1G97
Low-power configurable multiple function gate
74AUP1G97 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 10 — 28 March 2017
20 / 25
References
Outline
version
European
projection
Issue date
IEC JEDEC JEITA
SOT1255
sot1255_po
15-07-20
15-07-22
Unit
mm
max
nom
min
0.35 0.04 0.30 0.85
0.20 0.10 0.05
A
Dimensions (mm are the original dimensions)
X2SON6: plastic thermal enhanced extremely thin small outline package; no leads;
6 terminals; body 1.0 x 0.8 x 0.35 mm SOT1255
A
1
D
1.05
D
h
E e
1
e
2
b
0.25
L v y
0.05
y
1
0.32 0.02 0.25 0.80 0.60 0.401.00
0.170.220.30 0.00 0.22 0.750.95
0.250.30
0 1 mm
scale
A B
pin 1
ID area
X
L
(4x)
e
1
1 6
Dh
(2x)
3 4
52
e
2
A
B
v
D
E
C
y
C
y
1
detail X
A
A1
b
(4x)
Figure 26. Package outline SOT1255 (X2SON6)
Nexperia
74AUP1G97
Low-power configurable multiple function gate
74AUP1G97 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 10 — 28 March 2017
21 / 25
References
Outline
version
European
projection
Issue date
IEC JEDEC JEITA
SOT1454-1 - - -
sot1454-1_po
15-11-16
14-12-16
Unit
mm
max
nom
min
0.100 0.68 0.47
0.15 0.05
A
Dimensions (mm are the original dimensions)
WLCSP6: wafer level chip-scale package, 6 bumps; 0.65 x 0.44 x 0.27 mm SOT1454-1
A
1
A
2
0.22
0.18
0.085 0.65 0.44 0.22
b D E e e
1
0.23
e
2
0.44
v w
0.05
y
0.1
y
1
0.070 0.62 0.41
0.30
0.27
0.24
0.20
0.085
0.055
0.070
X
detail X
0
scale
1 mm
A
E
B
D
e
2
e
e
1
b
AC BØ v
CØ w
21
B
C
y
A
A
2
A
1
C
A
ball A1
index area
ball A1
index area
C
y
1
Figure 27. Package outline SOT1454-1 (WLCSP6)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

74AUP1G97GXZ

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Buy 74AUP1G97GXZ
Manufacturer:
Nexperia
Description:
Logic Gates 74AUP1G97GX/X2SON6/REEL 7" Q2/
Lifecycle:
New from this manufacturer.
Delivery:
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