XC95288XV-10CS280C

XC95288XV High-Performance CPLD
4 www.xilinx.com DS050 (v3.0) June 25, 2007
Product Specification
R
Supported I/O Standards
The XC95288XV CPLD features both LVCMOS and LVTTL
I/O implementations. See Table 1 for I/O standard voltages.
The LVTTL I/O standard is a general purpose EIA/JEDEC
standard for 3.3V applications that use an LVTTL input
buffer and Push-Pull output buffer. The LVCMOS2 standard
is used in 2.5V applications.
XC9500XV CPLDs are also 1.8V I/O compatible. The
X25TO18 setting is provided for generating 1.8V compatible
outputs from a CPLD normally operating in a 2.5V environ-
ment. The ISE software automatically groups outputs with
matching IOSTANDARD settings into the same V
CCIO
bank
when no location constraints are specified. The default I/O
Standard for pads without IOSTANDARD attributes is
LVTTL for XC9500XV devices.
Absolute Maximum Ratings
Recommended Operation Conditions
Table 1: IOSTANDARD Options
IOSTANDARD V
CCIO
LVTTL 3.3V
LVCMOS2 2.5V
X25TO18 1.8V
Symbol Description Value Units
V
CC
Supply voltage relative to GND –0.5 to 2.7 V
V
CCIO
Supply voltage for output drivers –0.5 to 3.6 V
V
IN
Input voltage relative to GND
(1)
–0.5 to 3.6 V
V
TS
Voltage applied to 3-state output
(1)
–0.5 to 3.6 V
T
STG
Storage temperature (ambient) –65 to +150
o
C
T
J
Junction temperature +150
o
C
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0V or overshoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
3. For solder specifications, see Xilinx Packaging
.
Symbol Parameter Min Max Units
V
CCINT
Supply voltage for internal logic
and input buffers
Commercial T
A
= 0
o
C to +70
o
C 2.37 2.62 V
Industrial T
A
= –40
o
C to +85
o
C 2.37 2.62
V
CCIO
Supply voltage for output drivers for 3.3V operation 3.0 3.6 V
Supply voltage for output drivers for 2.5V operation 2.37 2.62 V
Supply voltage for output drivers for 1.8V operation 1.71 1.89 V
V
IL
Low-level input voltage 0 0.8 V
V
IH
High-level input voltage 1.7 3.6 V
V
O
Output voltage 0 V
CCIO
V
Product Obsolete/Under Obsolescence
XC95288XV High-Performance CPLD
DS050 (v3.0) June 25, 2007 www.xilinx.com 5
Product Specification
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Quality and Reliability Characteristics
DC Characteristics Over Recommended Operating Conditions
AC Characteristics
Symbol Parameter Min Max Units
T
DR
Data retention 20 - Years
N
PE
Program/Erase cycles (endurance) 1,000 - Cycles
V
ESD
Electrostatic Discharge (ESD) 2,000 - Volts
Symbol Parameter Test Conditions Min Max Units
V
OH
Output high voltage for 3.3V outputs I
OH
= –4.0 mA 2.4 - V
Output high voltage for 2.5V outputs I
OH
= –1.0 mA 2.0 - V
Output high voltage for 1.8V outputs I
OH
= –100 μA 90% V
CCIO
-V
V
OL
Output low voltage for 3.3V outputs I
OL
= 8.0 mA - 0.4 V
Output low voltage for 2.5V outputs I
OL
= 1.0 mA - 0.4 V
Output low voltage for 1.8V outputs I
OL
= 100 μA-0.4V
I
IL
Input leakage current V
CC
= 2.62V
V
CCIO
= 3.6V
V
IN
= GND or 3.6V
10μA
I
IH
Input high-Z leakage current V
CC
= 2.62V
V
CCIO
= 3.6V
V
IN
= GND or 3.6V
10μA
V
CC
min < V
IN
< 3.6V - ±150 μA
C
IN
I/O capacitance V
IN
= GND
f = 1.0 MHz
-10pF
I
CC
Operating supply current
(low power mode, active)
V
I
= GND, No load
f = 1.0 MHz
59 mA
Symbol Parameter
XC95288XV-6 XC95288XV-7 XC95288XV-10
UnitsMin Max Min Max Min Max
T
PD
I/O to output valid - 6.0 - 7.5 - 10 ns
T
SU
I/O setup time before GCK 4.0 - 4.8 - 6.5 - ns
T
H
I/O hold time after GCK 0 - 0 - 0 - ns
T
CO
GCK to output valid - 3.8 - 4.5 - 5.8 ns
f
SYSTEM
Multiple FB internal operating
frequency
- 208 - 125.0 - 100.0 MHz
T
PSU
I/O setup time before p-term clock
input
1.0 - 1.6 - 2.1 - ns
T
PH
I/O hold time after p-term clock input 2.6 - 3.2 - 4.4 - ns
T
PCO
P-term clock output valid - 6.8 - 7.7 - 10.2 ns
T
OE
GTS to output valid - 4.5 - 5.0 - 7.0 ns
T
OD
GTS to output disable - 4.5 - 5.0 - 7.0 ns
T
POE
Product term OE to output enabled - 8.4 - 9.5 - 11.0 ns
T
POD
Product term OE to output disabled - 8.4 - 9.5 - 11.0 ns
Product Obsolete/Under Obsolescence
XC95288XV High-Performance CPLD
6 www.xilinx.com DS050 (v3.0) June 25, 2007
Product Specification
R
T
AO
GSR to output valid - 10.8 - 12.0 - 14.5 ns
T
PAO
P-term S/R to output valid - 11.8 - 12.6 - 15.3 ns
T
WLH
GCK pulse width (High or Low) 2.4 - 4.0 - 5.0 - ns
T
PLH
P-term clock pulse width (High or Low) 6.0 - 6.5 - 7.0 - ns
T
APRPW
Asynchronous preset/reset pulse width
(High or Low)
6.0 - 6.5 - 7.0 - ns
Symbol Parameter
XC95288XV-6 XC95288XV-7 XC95288XV-10
UnitsMin Max Min Max Min Max
Product Obsolete/Under Obsolescence

XC95288XV-10CS280C

Mfr. #:
Manufacturer:
Xilinx
Description:
Field-Programmable Gate Array
Lifecycle:
New from this manufacturer.
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