13/23
SERCON816
3.5.5 Read Access of Dual Port RAM
Figure 9. Read Access of Dual Port RAM
Notes: 1. Setup time input signals to falling edge RDN (Intel or Motorola mode with low active strobe) or rising edge RDN (Motorola mode
with high active strobe)
Symbol Parameter Min. Typ. Max. Unit
t
ASU
Setup time A11-0, (Note 1) 10 ns
Setup time MCSN0-1, if both signals are activated
simultaneously. (Note 1)
5ns
Setup time MCSN0-1, if one of these both signals is activated
10 ns earlier. (Note 1)
0ns
Setup time BHEN, WRN (only Motorola mode), (Note 1) 0 ns
t
AHD
hold time A11-0, BHEN, MCSN0-1, WRN (only Motorola
mode) to rising edge RDN (Intel Motorola mode with low
active strobe) or falling edge RDN (Motorola mode with high
active strobe)
0ns
t
RDNCLK
Cycle time of RAM read clock
SBAUD16 = 1 (f
RDNCLK
= f
SCLK
) 1 / f
SCLK
SBAUD16 = 0 (f
RDNCLK
= 2 * f
SCLK
)
0.5 / f
SCLK
t
MRDD
access time RDN to D15-0 valid
2 * t
RDNCLK
+ 30
ns
t
MBSY
delay RDN to BUSYN low 15 ns
t
MBHD
Delay BUSYN high to D15-0 valid
2 * t
RDNCLK
+ 30
ns
t
RDZ
Delay RDN to D15-0 high-Z 20 ns
t
RD1
RDN and WRN high after end of read access 15 ns
A10-0, BHEN,
MCSN0-1,
WRN (M o to ro l a m od e )
RD N
D15-0
BUSYN
t
M BSY
t
MBHD
t
RD Z
t
RD 1
t
MRDD
t
ASU
t
AHD
SERCON816
14/23
3.5.6 Write Access to Control Registers
Figure 10. Write Access to Control Registers
Notes: 1. Setup time input signals to falling edge WRN (Intel mode) or RDN (Motorola mode with low active strobe) or rising edge RDN (Mo-
torola mode with high active strobe)
Symbol Parameter Min. Typ. Max. Unit
t
ASU
Setup time A6-0, (Note 1) 10 ns
Setup time BHEN, PCSN0, PCS1, DMAACKNR, WRN (only
Motorola mode),
(Note 1)
0ns
t
AHD
hold time A6-0, BHEN, PCSN0, PCS1, DMAACKNT, WRN
(only Motorola mode) to rising edge WRN (Intel mode) or
RDN (Motorola mode, strobe active low) or falling edge RDN
(Motorola mode, strobe active high)
0ns
t
PWRW
pulse width WRN (Intel mode) or RDN (Motorola mode) 20 ns
t
DSU
setup time D15-0 to end of write access 10 ns
t
DHD
hold time D15-0 to end of write access 5 ns
t
PRQ
delay WRN or RDN to DMAREQT low 20 ns
A6-0, BHEN,
PC SN0 , PC S1 ,
DMAACKNT,
WRN (M o t o ro la m o d e )
WRN(Intel mode)
RDN(Motorola mode)
D15-0
DMAREQT
t
PRQ
t
DHD
t
DSU
t
PWRW
t
AHD
t
ASU
15/23
SERCON816
3.5.7 Write Access to DUAL Port RAM
Figure 11. Write Access to DUAL Port RAM
Notes: 1. Setup time input signals to falling edge WRN (Intel mode) or RDN (Motorola mode with low active strobe) or rising edge RDN (Mo-
torola mode with high active strobe)
Symbol Parameter Min. Typ. Max. Unit
t
ASU
Setup time A11-0, (Note 1) 10 ns
Setup time MCSN0-1, if both signals are activated
simultaneously. (Note 1)
5ns
Setup time MCSN0-1, if one of these both signals is activated
10 ns earlier. (Note 1)
0
Setup time BHEN, WRN (only Motorola mode), (Note 1) 0 ns
t
AHD
hold time A11-0, BHEN, MCSN0-1, WRN (only Motorola
mode) to rising edge of WRN (Intel mode) or RDN (Motorola
mode with low active strobe) or falling edge RDN (Motorola
mode with high active strobe)
0ns
t
MWRW
Pulse width WRN or RDN 20 ns
t
DSU
Setup time D15-0 to end of write access 10 ns
t
DHD
Hold time D15-0 after end of write access 5 ns
t
MBSY
Delay WRN or RDN (begin of write access) to BUSYN low 15 ns
t
MBHWH
Setup time BUSYN high to end of write access 15 ns
t
WR1
WRN and RDN high after end of write access 15 ns
A10-0, BHEN,
MCSN0-1,
WRN (M o to ro l a m o d e )
WRN (Intel mode)
RDN(Motorola mode)
D15-0
BUSYN
t
MBSY
t
MBHWH
t
MWRW
t
DSU
t
DHD
t
WR1
t
ASU
t
AHD

SERC816

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Telecom Interface ICs SERCOS Interfce Cont
Lifecycle:
New from this manufacturer.
Delivery:
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