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SERC816

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
7/23
SERCON816
3 ELECTRICAL (DC AND AC) CHARACTERISTICS
3.1 Absolute Maximum Ratings
WDOGN 24 O Watchdog output (active low)
L_ERRN 32 O Line error, active low: goes low when signal distortion is too high or when the
receive signal is missing. The operating mode is programmed by the
processor.
CYC_CLK 34 I SERCOS interface cycle clock: CYC_CLK synchronizes the communication
cycles. The polarity is programmable.
CON_CLK 35 O Control clock: becomes active within a communication cycle. Time, polarity
and width are programmable.
DIV_CLK 36 O Divided control clock: becomes active several times within a communication
cycle or once in several communication cycles. Number of pulses, start time,
repetition rate and polarity are programmable, the pulse width is 1 µs.
SCLK 2 I Serial clock for clock regeneration: the maximum frequency is 64 MHz.
SCLKO2 6 O Clock output: outputs the SCLK clock divided by 2 or 1.
SCLKO4 5 O Clock output: outputs the SCLK clock divided by 4 or 2.
MCLK 4 I Master clock for telegram processing and timing control, frequency 12 to 64
MHz.
RSTN 10 I Reset, active low. Must be zero for at least 50 ns after power on.
TEST 7 I Test, active high. Has to be tied to VSS.
OUTZ 11 I Puts outputs into high impedance state, active high: OUTZ is 1 puts all pins
into a high impedance state. The clocks are turned off and the circuit is reset.
For the in-circuit test and for turning on the power-down mode.
NDTRO 9 O NAND tree output. For the test at the semiconductor manufacturers and for
the connection test after board production. NDTRO is not set to a high
impedance state.
VSS 3,15,23,33
,42,50,60,
70,81,91
Ground pins:
VDD 1,8,19,27,
37,55,65,
76,86
Power supply +5 V ± 5%.
Symbol Parameter Value Unit
V
DD
Supply voltage -0.5 to 6.5 V
V
I
Input voltage -0.5 to V
DD
+ 0.5 V
V
O
Output voltage -0.5 to V
DD
+ 0.5 V
T
STG
Storage temperature -55 to +150 °C
Table 1. SERCON816 I/O Port Function Summary (continued)
Signal(s) Pin(s) IO Function
SERCON816
8/23
3.2 Recommended Operating Conditions
Notes: 1. Only if PLL is used (SBAUD16=0)
2. For normal operation, during testing f
MCLK
= 0 is possible
Symbol Parameter Min. Max. Unit
T
A
Operating temperature -40 85 °C
T
J
Chip junction temperature -40 125 °C
V
DD
Operating supply voltage 4.75 5.25 V
f
SCLK
Clock frequency SCLK
32
1
64 MHz
f
MCLK
Clock frequency MCLK
12
2
64 MHz
3.3 ELECTRICAL CHARACTERISTCS
(V
DD
= 5V ± 5% T
amb
= -40 °C to +85 °C, unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
V
IL
Low level input voltage (TTL)
All inputs
0.8 V
V
IH
High level input voltage (TTL)
All inputs
2.0 V
V
hyst
Schmitt trigger hysteresis
L_ERRN, TXD6-1, MCLK, SCLK,
RSTN, ADMUX, BUSMODE1-0,
BUSWIDTH, BYTEDIR, TM1-0,
SBAUD16, SBAUD, TEST, OUTZ,
RXD, CYC_CLK
0.4 0.7 V
I
IL
Low level input current with pull-
up
D15-0, A15-0, TXD6-1, ADMUX,
BUSMODE1-0, BYTEDIR, TM1-
0, SBAUD16, SBAUD, TEST,
OUTZ, RXD, CYC_CLK, BHEN,
MCSN1-0, PCSN0, PCS1,
DMAACKTN, DMAACKRN
V
I
= V
SS
-40 -100 -240 µA
I
IH
High level input current with pull-
down
MCLK, SCLK, RSTN, ALEH,
ALEL
V
I
= V
DD
40 100 240 µA
Rup Equivalent pull-up resistance V
I
= V
SS
23 50 112.5 KOhm
Rdn Equivalent pull-down resistance V
I
= V
DD
23 50 112.5 KOhm
V
OL
Low level output voltage, all O-
and I/O-pins except TXD6-1,
L_ERRN
I
OI
= -4 mA 0.4 V
V
OH
High level output voltage, all O-
and I/O-pins except TXD6-1,
L_ERRN
I
OH
= +4 mA 2.4 V
9/23
SERCON816
Notes: 1. estimated
3.4.1 Power Dissipation Considerations
Most of the current consumed by CMOS devices is alternate current (AC) which is charging and discharg-
ing the capacitances of the pins and internal nodes. The current consumption rises with the frequency at
which the pins and internal nodes will toggle and with the capacitances connected to the pins of the device:
P = f · C · V
2
(C=capacitance, V=voltage, f=frequency)
For applications which require low power consumption or exceeds the maximum allowed power consump-
tion the following is required:
– Connect unused pins to pull-up or pull-down resistors
– Minimize the capacitive load on the pins
– Reduce clock frequency of SCLK and MCLK
– Minimize accesses to the internal RAM and control registers
The maximum allowed power consumption is limited by the maximum allowed chip junction temperature
and by the number of VCC/VDD pins. The chip junction temperature is influenced by the ambient temper-
ature and the package thermal resistance. The ambient temperature could be influenced by the applica-
tion through a good temperature management like heat sinks or ambient air cooling.
V
OL
Low level output voltage, pins
TXD6-1, L_ERRN
I
OI
= -8 mA 0.4 V
V
OH
High level output voltage, pins
TXD6-1, L_ERRN
I
OH
= +8 mA 2.4
I
OZ
Tri-state output leakage V
O
= 0 V or V
DD
1 µA
I
KLU
I/O latch-up current V<V
SS
V>V
DD
200 mA
V
ESD
Electrostatic protection Leakage < 1 µA, human body
model
2000 V
C
PIN
Pin capacitance 10 pF
3.4 Power Dissipation
(V
DD
= 5V ± 5% T
amb
= -40 °C to +85 °C, unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
P
D
Power dissipation 16 Mbaud, MCLK=64 MHz
850
1
mW
P
DA
Maximum allowed power
dissipation
T
A
=+85°, no air flow 1000 mW
3.3 ELECTRICAL CHARACTERISTCS (continued)
(V
DD
= 5V ± 5% T
amb
= -40 °C to +85 °C, unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

SERC816

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Manufacturer:
STMicroelectronics
Description:
Telecom Interface ICs SERCOS Interfce Cont
Lifecycle:
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