Should the packet remain unclassified, the traffic is retried with an error in the case of Type 10 and 11 traffic and dropped in
the case of Type 9 traffic. Dropped traffic is logged and upon a threshold can assert an error interrupt.
Classification allows Type 9, 10 and 11 traffic to be distributed across 64 possible Frame queues. A single dedicated inbound
Type 8 Port-write Frame queue is provided. For all outbound traffic types (Type 8, 9, 10 and 11), the Data Path Acceleration
Architecture allows a very large number of outbound Frame queues effectively limited by system, software and performance
constraints.
The RMan is DPAA entity designed to work in conjunction with the chip's Serial RapidIO controllers. This figure illustrates
RMan use cases.
Figure 5. RMan use cases
Inbound Serial RapidIO traffic, including messages (Type 11), doorbells (Type 10), and data (Type 9) are classified by the
RMan and enqueued to a configured FQ, allowing the DPAA to deliver the "data" to any DPAA consumer, including vCPUs,
accelerators, or Ethernet ports (FMan). Outbound traffic enqueued to the RMan for transmission is given a configured ID,
allowing the target FQ on the receiving device to be identified. The RMan/Serial RapidIO combination is particularly useful
for chip-to-chip communication, with an x4 Serial RapidIO interface providing up to 16 Gbps of data/message bandwidth
between RMan enabled QorIQ chips.
4.10.2.6 SEC 5.2
The SEC 5.2 can perform full protocol processing for the following security protocols:
IPsec
SSL/TLS
3GPP RLC encryption/decryption
LTE PDCP
SRTP
IEEE 802.1AE MACSec
IEEE 802.16e WiMax MAC layer
The SEC 5.2 supports the following algorithms, modes, and key lengths as raw modes, or in combination with the security
protocol processing described above.
Chip features
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16 Freescale Semiconductor, Inc.
Public-key hardware accelerators (PKHA)
RSA and Diffie-Hellman (to 4096b)
Elliptic curve cryptography (1023b)
Data-encryption standard accelerators (DESA)
DES, 3DES (2-key, 3-key)
ECB, CBC, OFB, and CFB modes
Advanced-encryption standard accelerators (AESA)
Key lengths of 128-bit, 192-bit, and 256-bit
Confidentiality modes
ECB, CBC, OFB, CFB, CTR and XTS
Authenticated encryption modes
CCM and GCM
ARC four hardware accelerators (AFHA)
Compatible with RC4 algorithm
Message digest hardware accelerators (MDHA)
SHA-1, SHA-256, 384, 512-bit digests
MD5 128-bit digest
HMAC with all algorithms
Kasumi/F8 hardware accelerators (KFHA)
F8, F9 as required for 3GPP
A5/3 for GSM and EDGE, GEA-3 for GPRS
Snow 3G hardware accelerators (STHA)
Implements Snow 3.0, F8 and F9 modes
ZUC Hardware Accelerators (ZHA)
Implements 128-EEA3 & 128-EIA3
CRC Unit
Standard and user-defined polynomials
Random-number generator (RNG)
Incorporates TRNG entropy generator for seeding and deterministic engine (SHA-256)
Supports random IV generation
DTLS
IEEE Std 802.11 WiFi
Protocol Cipher suite Performance (aggregate
encap and decap)
IPsec AES-CBC/AES-XCBC-MAC 4.4 Gbps
LTE PDCP U-plane 128-EEA2 (AES) 8.8 Gbps
LTE PDCP C-plane 128-EEA3 and 128-EIA3
(ZUC)
3.5 Gbps
The SEC dequeues data from its QMan hardware portal and, based on FQ configuration, also dequeues associated
instructions and operands in the Shared Descriptor. The SEC processes the data then enqueues it to the configured output FQ.
The SEC uses the Status/CMD word in the output Frame Descriptor to inform the next consumer of any errors encountered
during processing (for example, received packet outside the anti-replay window.)
The SEC 5.2 is also part of the QorIQ Platform's Trust Architecture, which gives the SoC the ability to perform secure boot,
runtime code integrity protection, and session key protection. The Trust Architecture is described in Resource partitioning
and QorIQ Trust Architecture.
Chip features
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Freescale Semiconductor, Inc. 17
4.10.2.7 Decompression and Compression Engine (DCE 1.0)
The Decompression and Compression Engine (DCE 1.0) is an accelerator compatible with Datapath Architecture providing
lossless data decompression and compression for the QorIQ family of SoCs. The DCE supports the raw DEFLATE algorithm
(RFC1951), GZIP format (RFC1952) and ZLIB format (RFC1950). The DCE also supports Base 64 encoding and decoding
(RFC4648).
The DEFLATE algorithm is a basic building block for data compression in most modern communication systems. It is used
by HTTP to compress web pages, by SSL to compress records, by gzip to compress files and email attachments, and by many
other applications.
Deflate involves searching for repeated patterns previously seen in a Frame, computing the length and the distance of the
pattern with respect to the current location in the Frame, and encoding the resulting information into a bitstream.
The decompression algorithm involves decoding the bitstream and replaying past data. The Decompression and Compression
Engine is architected to minimize the system memory bandwidth required to do decompression and compression of Frames
while providing multi-gigabits per second of performance.
Detailed features include the following:
Deflate; as specified as in RFC1951
GZIP; as specified in RFC1952
Zlib; as specified in RFC1950
Interoperable with the zlib 1.2.5 compression library
Compression
ZLIB, GZIP and DEFLATE header insertion
ZLIB and GZIP CRC computation and insertion
Zlib sync flush and partial flush for chunked compression (for example, for HTTP1.1)
Four modes of compression
No compression (just add DEFLATE header)
Encode only using static/dynamic Huffman codes
Compress and encode using static Huffman codes
Compress and encode using dynamic Huffman codes
Uses a 4KB sliding history window
Supports Base 64 encoding (RFC4648) after compression
Provides at least 2.5:1 compression ratio on the Calgary Corpus
Decompression supports:
ZLIB, GZIP and DEFLATE header removal
ZLIB and GZIP CRC validation
32KB history
Zlib flush for chunked decompression (for HTTP1.1 for example)
All standard modes of decompression
No compression
Static Huffman codes
Dynamic Huffman codes
Provides option to return original compressed Frame along with the uncompressed Frame or release the buffers to
BMan
Does not support use of ZLIB preset dictionaries (FDICT flag = 1 is treated as an error).
Base 64 decoding (RFC4648) prior to decompression
The DCE 1.0 is designed to support up to 8.8 Gbps for either compression or decompression, or 17.5 Gbps aggregate at ~4
KB data sizes.
4.11 OCeaN DMA
The OCeaN fabric is used to:
Chip features
T2080 Product Brief, Rev 0, 04/2014
18 Freescale Semiconductor, Inc.

T2081NSN7MQB

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Microprocessors - MPU QorIQ, 64b Power Arch, 8x 1.2GHz threads, 1.6GT/s DDR3/3L, 2x10GE, crypto disabled, 0-105C, Rev 1.1
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New from this manufacturer.
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