Power Architecture
e6500
Power Architecture
e6500
Power Architecture
e6500
Power Architecture
e6500
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
2 MB Banked L2
(peripheral access management unit)
CoreNet
TM
Coherency Fabric
MPIC
PreBoot Loader
Security Monitor
Internal BootROM
Power mgmt
SDXC/eMMC
eSPI
2 x DUART
IFC
Clocks/Reset
GPIO
CCSR
512 KB
Plat Cache
64-bit DDR3/3L
with ECC
PAMU
PAMU
PAMU
2 x USB2.0 w/PHY
4x I
2
C
Pre-Fetch
SEC
PME
QMan
BMan
DCE
FMan
Parse, classify,
distribute
Buffer
2x 2.5/10G
DMAx3
PCIe
PCle
PCle
PCle
8 lanes up to 10 GHz SerDes
1GE
1GE
1GE
1GE
DCB
1GE
1GE
Real-time
debug
Watch point
cross-
trigger
Perf
Monitor
CoreNet
trace
Figure A-1. T2081 block diagram
A.2 Overview of Differences
Table A-1. Comparison between T2080 and T2081
Feature T2080 T2081
Peripherals
10G Ethernet Controllers Up to four with XFI, 10GBase-
KR, 10GBase-KX, XAUI, HiGig
and HiGig2
Up to two XFI or 10GBase-KR,
10GBase-KX
1G Ethernet Controllers Up to eight Up to six
SerDes and Pinout
Total number of SerDes lanes 16 8
High Speed Serial IO
SRIO Controller and RapidIO Message Manager 2 + RMan not supported
SATA Controller 2 not supported
Aurora supported not supported
Package 25 x 25mm, 896 pins, 0.8mm
pitch
23 x 23mm, 780 pins, 0.8mm
pitch, pin compatible with
T1042
Overview of Differences
T2080 Product Brief, Rev 0, 04/2014
Freescale Semiconductor, Inc. 25
A.3 RCW Fields
The table below points out the deviation of T2081 from T2080
RCW
Field
Name Description
136-143 SRDS_PRTCL_S2 Reserved
162-163 SRDS_PLL_REF _CLK_SEL_S2 Reserved
170-171 SRDS_PLL_PD_ S2 Reserved
178 SRDS_DIV_SRIO_S2 Reserved
180 SRDS_DIV_AURORA_S2 Reserved
181-182 SRDS_DIV_PEX _S2 Reserved
196-200 BOOT_LOC 1_1000 Reserved (SRIO1)
0_1001 Reserved (SRIO 2)
260-262 RIO_DEVICE_ID 011-Reserved
101-Reserved
111-Reserved
263 RIO_SYS_SIZE Reserved
267 HOST_AGT_SRIO Reserved
268 RIO_RESPOND _ONLY Reserved
A.4 T2081 Registers
This section points out the deviation of registers from T2080
Table A-3. Unavailable register bits
Register Name Bit Number Description
Device Disable Register 1 (DCFG_DEVDISR1) 24 (RMan) Set to disable
Device Disable Register 1 (DCFG_DEVDISR1) 16-17 (SATA) Set to disable
Device Disable Register 3 (DCFG_DEVDISR3) 4-5 (SRIO) Set to disable
Device Disable Register 5 (DCFG_DEVDISR5) 11 (NAL) Set to disable
References to SerDes 2 registers should be disregarded for T2081.
Table A-4. SVR, PCI and RapidIO Device IDs, JTAG ID
SVR PCI and RapidIO Device IDs JTAG ID
T2081 with security 0x 8539_0010 0x0838 018E601D
T2081 without security 0x 8531_0010 0x0839 018E601D
RCW Fields
T2080 Product Brief, Rev 0, 04/2014
26 Freescale Semiconductor, Inc.
A.5 T2081 Signal Differences
SerDes 2 signals described in Signals Overview are not supported on T2081.
A.6 SerDes Assignments
The following notation conventions are used in the table:
XFIm indicates XFI (1 lane @10.3125 Gbps), “m” indicates MAC on the Frame Manager. For example, “XFI9”
indicates XFI using MAC 9.
SGMII notation :
sgm means SGMII @ 1.25 Gbps where “m” indicates which MAC on the Frame Manager. For example, “SG3”
indicates SGMII for MAC 3 at 1.25 Gbps.
sgm means SGMII @3.125Gbps where “m” indicates which MAC on the Frame Manager. For example, “SG3
indicates SGMII for MAC 3 at 3.25 Gbps.
PCIe notation :
PCIem is PCIe @ 5/2.5 Gbps, m indicates the PCIe controller number.
PCIem is PCIe @ 8/5/2.5 Gbps, m indicates the PCIe controller number.
Per lane PLL mapping: 1-PLL1, 2-PLL2
SerDes Networking Options:
Table A-5. SerDes
SRDS_PR
TCL_S1
A B C D E F G H Per lane
PLL
mapping
6E XFI9 XFI10 SG1 SG2 PEX4 SG5 SG6 11222222
AA PEX3 PEX4 11111111
BC PEX3 SG1 SG2 PEX4 11111111
C8 PEX3 SG10 SG1 SG2 PEX4 SG5 SG6 11221111
CA PEX3 SG10 SG1 SG2 PEX4 SG4 SG5 SG6 11221111
D6 PEX3 SG10 SG1 SG2 PEX4 SG5 SG6 11112211
DE PEX3 PEX4 PEX1 PEX2 SG6 11111111
E0 PEX3 PEX4 PEX1 SG5 SG6 11111111
F2 PEX3 SG10 SG1 SG2 PEX4 PEX1 PEX2 SG6 11111111
F8 PEX3 SG10 SG1 SG2 PEX4 PEX1 PEX2 SG6 11221111
FA PEX3 SG10 SG1 SG2 PEX4 PEX1 SG5 SG6 11221111
6C XFI9 XFI10 SG1 SG2 PEX4 11222222
70 XFI9 XFI10 SG1 SG2 PEX4 SG4 SG5 SG6 11222222
T2081 Signal Differences
T2080 Product Brief, Rev 0, 04/2014
Freescale Semiconductor, Inc. 27

T2081NSN7MQB

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Microprocessors - MPU QorIQ, 64b Power Arch, 8x 1.2GHz threads, 1.6GT/s DDR3/3L, 2x10GE, crypto disabled, 0-105C, Rev 1.1
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union