Table 2. Power architecture metrics (continued)
Metric Per core Full device
Double-precision GFLOPs 3.6 14.4
The core subsystem includes the following features:
• Up to 1.8 GHz
• Dual-thread with simultaneous multi-threading (SMT)
• 40-bit physical addressing
• L2 MMU
• Supporting 4 KB pages
• TLB0; 8-way set-associative, 1024-entries (4 KB pages)
• TLB1; fully associative, 64-entry, supporting variable size pages and indirect page table entries
• Hardware page table walk
• 64-byte cache line size
• L1 caches, running at core frequency
• 32 KB instruction, 8-way set-associative
• 32 KB data, 8-way set-associative
• Each with data and tag parity protection
• Hardware support for memory coherency
• Five integer units: 4 simple (2 per thread), 1 complex (integer multiply and divide)
• Two load-store units: one per thread
• Classic double-precision floating-point unit
• Uses 32 64-bit floating-point registers (FPRs) for scalar single- and double-precision floating-point arithmetic
• Designed to comply with IEEE Std. 754™-1985 FPU for both single and double-precision operations
• AltiVec unit
• 128-bit Vector SIMD engine
• 32 128-bit VR registers
• Operates on a vector of
• Four 32-bit integers
• Four 32-bit single precision floating-point units
• Eight 16-bit integers
• Sixteen 8-bit integers
• Powerful permute unit
• Enhancements include: Move from GPRs to VR, sum of absolute differences operation, extended support for
misaligned vectors, handling head and tails of vectors
• Supports Data Path Acceleration Architecture (DPAA) data and context "stashing" into L1 and L2 caches
• User, supervisor, and hypervisor instruction level privileges
• Addition of Elemental Barriers and "wait on reservation" instructions
• New power-saving modes including "drowsy core" with state retention and nap
• State retention power-saving mode allows core to quickly wake up and respond to service requests
• Processor facilities
• Hypervisor APU
• "Decorated Storage" APU for improved statistics support
• Provides additional atomic operations, including a "fire-and-forget" atomic update of up to two 64-bit
quantities by a single access
• Addition of Logical to Real Address translation mechanism (LRAT) to accelerate hypervisor performance
• Expanded interrupt model
• Improved Programmable Interrupt Controller (PIC) automatically ACKs interrupts
• Implements message send and receive functions for interprocessor communication, including receive
filtering
• External PID load and store facility
Chip features
T2080 Product Brief, Rev 0, 04/2014
6 Freescale Semiconductor, Inc.
