CAT24AA16
www.onsemi.com
2
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Storage Temperature −65 to +150 °C
Voltage on any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. REABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter Min Units
N
END
(Note 3) Endurance 1,000,000 Program/Erase Cycles
T
DR
Data Retention 100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode @ 25°C
Table 3. DC OPERATING CHARACTERISTICS (V
CC
= 1.7 V to 5.5 V, T
A
= −40°C to 85°C, unless otherwise specified.)
Symbol
Parameter Test Conditions Min Max Units
I
CCR
Read Current Read, f
SCL
= 400 kHz 0.5 mA
I
CCW
Write Current Write, f
SCL
= 400 kHz 1 mA
I
SB
Standby Current All I/O Pins at GND or V
CC
1
mA
I
L
I/O Pin Leakage Pin at GND or V
CC
1
mA
V
IL
Input Low Voltage −0.5 V
CC
x 0.3 V
V
IH
Input High Voltage V
CC
x 0.7 V
CC
+ 0.5 V
V
OL1
Output Low Voltage V
CC
w 2.5 V, I
OL
= 3.0 mA 0.4 V
V
OL2
Output Low Voltage V
CC
< 2.5 V, I
OL
= 1.0 mA 0.2 V
Table 4. PIN IMPEDANCE CHARACTERISTICS (V
CC
= 1.7 V to 5.5 V, T
A
= −40°C to 85°C, unless otherwise specified.)
Symbol Parameter Conditions Max Units
C
IN
(Note 4) SDA I/O Pin Capacitance V
IN
= 0 V 8 pF
C
IN
(Note 4) Input Capacitance (Other Pins) V
IN
= 0 V 6 pF
I
WP
(Note 5) WP Input Current
V
IN
< 0.5 x V
CC
, V
CC
= 5.5 V 200
mA
V
IN
< 0.5 x V
CC
, V
CC
= 3.3 V 150
V
IN
< 0.5 x V
CC
, V
CC
= 1.8 V 100
V
IN
> 0.5 x V
CC
1
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong;
therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull−down reverts to a weak current source.
