OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

CAT24AA16TDI-GT3

P1-P3P4-P6P7-P9P10-P11
CAT24AA16
www.onsemi.com
4
Power−On Reset (POR)
Each CAT24AA16 incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state. The device will power up into Standby
mode after V
CC
exceeds the POR trigger level and will
power down into Reset mode when V
CC
drops below the
POR trigger level.
This bi−directional POR behavior protects the device
against brown−out failure, following a temporary loss of
power.
Pin Description
SCL: The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA: The Serial Data I/O pin accepts input data and delivers
output data. In transmit mode, this pin is open drain. Data is
acquired on the positive edge, and delivered on the negative
edge of SCL.
WP: When the Write Protect input pin is forced HIGH by an
external source, all write operations are inhibited. When the
pin is not driven by an external source, it is pulled LOW
internally.
Functional Description
The CAT24AA16 supports the Inter−Integrated Circuit
(I
2
C) Bus protocol. The protocol relies on the use of a Master
device, which provides the clock and directs bus traffic, and
Slave devices which execute requests. The CAT24AA16
operates as a Slave device. Both Master and Slave can
transmit or receive, but only the Master can assign those
roles.
I
2
C Bus Protocol
The 2−wire I
2
C bus consists of two lines, SCL and SDA,
connected to the V
CC
supply via pullup resistors. The Master
provides the clock to the SCL line, and the Master and Slaves
drive the SDA line. A ‘0’ is transmitted by pulling a line
LOW and a ‘1’ by releasing it HIGH. Data transfer may be
initiated only when the bus is not busy (see AC
Characteristics). During data transfer, SDA must remain
stable while SCL is HIGH.
START/STOP Condition
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 2). A START is generated by a
HIGH to LOW transition, while a STOP is generated by a
LOW to HIGH transition. The START acts like a wake−up
call. Absent a START, no Slave will respond to the Master.
The STOP completes all commands.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8−bit Slave address
(Figure 3). The four most significant bits of the Slave
address are 1010 (Ah). The next three bits are internal
address bits, a
10
, a
9
, a
8
. The last bit, R/W, instructs the Slave
to either provide (1) or accept (0) data, i.e. it specifies a Read
(1) or a Write (0) operation.
Acknowledge
During the 9
th
clock cycle following every byte sent onto
the bus, the transmitter releases the SDA line, allowing the
receiver to respond. The receiver then either acknowledges
(ACK) by pulling SDA LOW, or does not acknowledge
(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
is illustrated in Figure 5.
START
CONDITION
STOP
CONDITION
SDA
SCL
Figure 2. Start/Stop Timing
1 0 1 0 a
10
a
9
a
8
R/W
Figure 3. Slave Address Bits
CAT24AA16
www.onsemi.com
5
189
START
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY
(RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK DELAY (v t
AA
)
ACK SETUP (w t
SU:DAT
)
Figure 4. Acknowledge Timing
t
HIGH
SCL
SDA IN
SDA OUT
t
LOW
t
F
t
LOW
t
R
t
BUF
t
SU:STO
t
SU:DAT
t
HD:DAT
t
HD:STA
t
SU:STA
t
AA
t
DH
Figure 5. Bus Timing
WRITE OPERATIONS
Byte Write
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/
W
bit set to ‘0’. The Master then sends an address
byte and a data byte and concludes the session by creating
a STOP condition on the bus. The Slave responds with ACK
after every byte sent by the Master (Figure 6). The STOP
starts the internal Write cycle, and while this operation is in
progress (t
WR
), the SDA output is tri−stated and the Slave
does not acknowledge the Master (Figure 7).
Page Write
The Byte Write operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 8). Up to 16 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
written to memory in a single internal Write cycle (t
WR
).
Acknowledge Polling
The acknowledge (ACK) polling routine can be used to
take advantage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT24AA16 initiates the internal write cycle.
The ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT24AA16 is still busy
with the write operation, NoACK will be returned. If the
CAT24AA16 device has completed the internal write
operation, an ACK will be returned and the host can then
proceed with the next read or write operation.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the Write
operation. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the 1
st
data byte
(Figure 9). If the WP pin is HIGH during the strobe interval,
the Slave will not acknowledge the data byte and the Write
request will be rejected.
Delivery State
The CAT24AA16 is shipped erased, i.e., all bytes are FFh.
CAT24AA16
www.onsemi.com
6
BUS ACTIVITY:
MASTER
SLAVE
S
S
ADDRESS
BYTE
DATA
BYTE
SLAVE
ADDRESS
S
A
C
K
P
a
7
B a
0
A
C
K
A
C
K
T
O
P
T
A
R
T
d
7
B d
0
Figure 6. Byte Write Sequence
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK8
th
Bit
Byte n
SCL
SDA
Figure 7. Write Cycle Timing
S
T
O
P
S
S
T
A
R
T
P
SLAVE
ADDRESS
n = 1
x v 15
ADDRESS
BYTE
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+x
BUS ACTIVITY:
MASTER
SLAVE
Figure 8. Page Write Sequence
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
1891 8
a
7
a
0
d
7
d
0
t
SU:WP
t
HD:WP
ADDRESS
BYTE
DATA
BYTE
SCL
SDA
WP
Figure 9. WP Timing
P1-P3P4-P6P7-P9P10-P11

CAT24AA16TDI-GT3

Mfr. #:
Buy CAT24AA16TDI-GT3
Manufacturer:
ON Semiconductor
Description:
EEPROM 16K-Bit I2C Serial
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet