1. General description
The TJA1102 is a 100BASE-T1 compliant dual-port Ethernet PHY optimized for
automotive use cases such as gateways, IP camera links, driver assistance systems and
back-bone networks. The device provides 100 Mbit/s transmit and receive capability over
two unshielded twisted-pair cables, supporting a cable length of up to at least 15 m. The
TJA1102 has been designed for automotive robustness, while minimizing power
consumption and system costs. For added flexibility, a single PHY version is available
(TJA1102S) in which one of the PHYs is disabled.
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2. Features and benefits
2.1 General
Dual-port 100BASE-T1 PHY
Single-port operation possible
MII- and RMII-compliant interfaces to the bus
HVQFN 56-pin package (
8 8mm)
2.2 Optimized for automotive use cases
Transmitter optimized for capacitive coupling to unshielded twisted-pair cable
Adaptive receive equalizer optimized for automotive cable length of up to at least 15 m
Enhanced integrated PAM-3 pulse shaping for low RF emissions
EMC-optimized output driver strength for MII and RMII
MDI pins protected against transients in automotive environment
MDI pins do not need external filtering or ESD protection
Automotive-grade temperature range from 40 C to +125 C
Automotive product qualification in accordance with AEC-Q100
2.3 Low-power mode
Dedicated PHY enable/disable input pin to minimize power consumption
Inhibit output for voltage regulator control
OPEN Alliance-compliant wake-up concept (global wake-up support)
Robust remote wake-up detection via bus lines
Wake-up forwarding on PHY level
OPEN Alliance-compliant sleep concept
TJA1102
100BASE-T1 dual/single PHY for automotive Ethernet
Rev. 1 — 1 November 2017 Product short data sheet
TJA1102_SDS All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product short data sheet Rev. 1 — 1 November 2017 2 of 19
NXP Semiconductors
TJA1102
100BASE-T1 Dual PHY for Automotive Ethernet
Local wake-up pin
Wake-up via SMI-access
2.4 Diagnosis
Real-time monitoring of link stability and transmitted data quality
Diagnosis of cable errors (shorts and opens)
Gap-free supply undervoltage detection with fail-silent behavior
Internal, external and remote loopback modes for diagnosis
2.5 Miscellaneous
Internal reverse MII mode for repeater operation
On-chip regulators to provide 3.3 V single-supply operation
Supports optional 1.8 V external supply for digital core
On-chip termination resistors for the differential cable pair
Jumbo frame support up to 16 kB
3. Ordering information
[1] Dual PHY.
[2] Single PHY.
Table 1. Ordering information
Type number Package
Name Description Version
TJA1102HN
[1]
HVQFN56 plastic thermal enhanced very thin quad flat package; no leads; 56
terminals; body 8 8 0.85 mm
SOT684-13
TJA1102SHN
[2]
TJA1102_SDS All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product short data sheet Rev. 1 — 1 November 2017 3 of 19
NXP Semiconductors
TJA1102
100BASE-T1 Dual PHY for Automotive Ethernet
4. Block diagram
A block diagram of the TJA1102 is shown in Figure 1. The 100BASE-T1 sections contain
the functional blocks specified in the 100BASE-T1 standard that make up the Physical
Coding Sublayer (PCS) and the Physical Medium Attachment (PMA) layer for both the
transmit and receive signal paths. The MII/RMII interface (including the Serial
Management Interface (SMI)) conforms to IEEE802.3 clause 22.
Additional blocks are defined for mode control, register configuration, interrupt control,
system configuration, reset control, local wake-up, remote wake-up, undervoltage
detection and configuration control. A number of power-supply-related functional blocks
are defined: an internal 1.8 V regulator for the digital core, a Very Low Power (VLP) supply
for Sleep mode, the reset circuit, supply monitoring and inhibit control.
The clock signals needed for the operation of the PHY are generated in the PLL block,
derived from an external crystal or an oscillator input signal.
Pin strapping allows a number of default PHY settings (e.g. Master or Slave configuration)
to be hardware-configured at power-up.

TJA1102HN/0Z

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Ethernet ICs TJA1102HN/HVQFN56//0/REEL 13 Q1 NDP SSB
Lifecycle:
New from this manufacturer.
Delivery:
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