TJA1102_SDS All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product short data sheet Rev. 1 — 1 November 2017 8 of 19
NXP Semiconductors
TJA1102
100BASE-T1 Dual PHY for Automotive Ethernet
5.2 MII and RMII
The TJA1102 supports a number of MII modes that can be selected via pin strapping or
the SMI. The PHYs should be configured to operate in the same mode, with common
clocking. The following modes are supported:
• MII
• RMII (25 MHz XTAL or external 50 MHz via REF_CLK)
• Reverse MII (connected externally or internally to the second PHY)
5.2.1 MII
The connections between the PHY and the MAC are shown in more detail in Figure 4.
Data is exchanged via 4-bit wide data nibbles on TXD[3:0] and RXD[3:0]. Transmit and
receive data is synchronized with the transmit (TXC) and receive (RXC) clocks. Both clock
signals are provided by the PHY and are typically derived from an external clock or crystal
running at a nominal frequency of 25 MHz (100 ppm). Normal data transmission is
initiated with a HIGH level on TXEN, while a HIGH level on RXDV indicates normal data
reception.
5.2.2 RMII
5.2.2.1 Signaling and encoding
RMII data is exchanged via 2-bit wide data nibbles on TXD[1:0] and RXD[1:0], as
illustrated in Figure 5
. To achieve the same data rate as MII, the interface is clocked at a
nominal frequency of 50 MHz. A single clock signal, REF_CLK, is provided for both
transmit and received data. This clock signal is provided by the PHY and is typically
derived from an external 25 MHz (100 ppm) crystal (see Figure 5
(a)). Alternatively, a
50 MHz clock signal (50 ppm) generated by an external oscillator can be connected to
pin REF_CLK (see Figure 5
(b)). A third option is to connect a 25 MHz (100 ppm) clock
signal generated by another PHY or switch to pin CLK_IN_OUT (see Figure 5
(c)).
a. Using external XTAL showing optional 25 MHz
clock output
b. Using external reference clock
Fig 4. MII signaling
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