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TSL2563FN

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
TSL2562, TSL2563
LOW-VOLTAGE
LIGHT-TO-DIGITAL CONVERTER
TAOS066N − AUGUST 2010
10
r
r
Copyright E 2010, TAOS Inc.
The LUMENOLOGY r Company
www.taosinc.com
PRINCIPLES OF OPERATION
Analog-to-Digital Converter
The TSL256x contains two integrating analog-to-digital converters (ADC) that integrate the currents from the
channel 0 and channel 1 photodiodes. Integration of both channels occurs simultaneously, and upon completion
of the conversion cycle the conversion result is transferred to the channel 0 and channel 1 data registers,
respectively. The transfers are double buffered to ensure that invalid data is not read during the transfer. After
the transfer, the device automatically begins the next integration cycle.
Digital Interface
Interface and control of the TSL256x is accomplished through a two-wire serial interface to a set of registers
that provide access to device control functions and output data. The serial interface is compatible with System
Management Bus (SMBus) versions 1.1 and 2.0, and I
2
C bus Fast-Mode. The TSL256x offers three slave
addresses that are selectable via an external pin (ADDR SEL). The slave address options are shown in Table 1.
Table 1. Slave Address Selection
ADDR SEL TERMINAL LEVEL SLAVE ADDRESS SMB ALERT ADDRESS
GND 0101001 0001100
Float 0111001 0001100
VDD 1001001 0001100
NOTE: The Slave and SMB Alert Addresses are 7 bits. Please note the SMBus and I
2
C protocols on pages 9 through 12. A read/write bit should
be appended to the slave address by the master device to properly communicate with the TSL256X device.
SMBus and I
2
C Protocols
Each Send and Write protocol is, essentially, a series of bytes. A byte sent to the TSL256x with the most
significant bit (MSB) equal to 1 will be interpreted as a COMMAND byte. The lower four bits of the COMMAND
byte form the register select address (see Table 2), which is used to select the destination for the subsequent
byte(s) received. The TSL256x responds to any Receive Byte requests with the contents of the register
specified by the stored register select address.
The TSL256X implements the following protocols of the SMB 2.0 specification:
D Send Byte Protocol
D Receive Byte Protocol
D Write Byte Protocol
D Write Word Protocol
D Read Word Protocol
D Block Write Protocol
D Block Read Protocol
The TSL256X implements the following protocols of the Philips Semiconductor I
2
C specification:
D I
2
C Write Protocol
D I
2
C Read (Combined Format) Protocol
TSL2562, TSL2563
LOW-VOLTAGE
LIGHT-TO-DIGITAL CONVERTER
TAOS066N − AUGUST 2010
11
The LUMENOLOGY r Company
r
r
Copyright E 2010, TAOS Inc.
www.taosinc.com
When an SMBus Block Write or Block Read is initiated (see description of COMMAND Register), the byte
following the COMMAND byte is ignored but is a requirement of the SMBus specification. This field contains
the byte count (i.e. the number of bytes to be transferred). The TSL2562 (SMBus) device ignores this field and
extracts this information by counting the actual number of bytes transferred before the Stop condition is
detected.
When an I
2
C Write or I
2
C Read (Combined Format) is initiated, the byte count is also ignored but follows the
SMBus protocol specification. Data bytes continue to be transferred from the TSL2563 (I
2
C) device to Master
until a NACK is sent by the Master.
The data formats supported by the TSL2562 and TSL2563 devices are:
D Master transmitter transmits to slave receiver (SMBus and I
2
C):
− The transfer direction in this case is not changed.
D Master reads slave immediately after the first byte (SMBus only):
− At the moment of the first acknowledgment (provided by the slave receiver) the master transmitter
becomes a master receiver and the slave receiver becomes a slave transmitter.
D Combined format (SMBus and I
2
C):
− During a change of direction within a transfer, the master repeats both a START condition and the slave
address but with the R/W bit reversed. In this case, the master receiver terminates the transfer by
generating a NACK on the last byte of the transfer and a STOP condition.
For a complete description of SMBus protocols, please review the SMBus Specification at
http://www.smbus.org/specs. For a complete description of I
2
C protocols, please review the I
2
C Specification
at http://www.semiconductors.philips.com.
Wr
7
Data ByteSlave AddressS
1
APA
811 11
XX
A Acknowledge (this bit position may be 0 for an ACK or 1 for a NACK)
P Stop Condition
Rd Read (bit value of 1)
S Start Condition
Sr Repeated Start Condition
Wr Write (bit value of 0)
X Shown under a field indicates that that field is required to have a value of X
... Continuation of protocol
Master-to-Slave
Slave-to-Master
Figure 9. SMBus and I
2
C Packet Protocol Element Key
TSL2562, TSL2563
LOW-VOLTAGE
LIGHT-TO-DIGITAL CONVERTER
TAOS066N − AUGUST 2010
12
r
r
Copyright E 2010, TAOS Inc.
The LUMENOLOGY r Company
www.taosinc.com
Wr
7
Data ByteSlave AddressS
1
APA
811 11
Figure 10. SMBus Send Byte Protocol
Rd
7
Data ByteSlave AddressS
1
APA
811 11
1
Figure 11. SMBus Receive Byte Protocol
Wr
7
Data ByteSlave AddressS
1
AAA
811 1 8
Command Code
1
P
1
Figure 12. SMBus Write Byte Protocol
Wr
7
Data Byte LowSlave AddressS
1
A A
811 1
Command Code
1
P
811
RdSlave AddressS A A
7 1
1
1
Figure 13. SMBus Read Byte Protocol
Wr
7
Data Byte LowSlave AddressS
1
AAA
811 1 8
Command Code
1
PData Byte High A
811
Figure 14. SMBus Write Word Protocol
Wr
7
Data Byte LowSlave AddressS
1
A A
811 1
Command Code
1
PData Byte High A
811
RdSlave AddressS A A
...
7 1
811
1
Figure 15. SMBus Read Word Protocol
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42

TSL2563FN

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Buy TSL2563FN
Manufacturer:
ams
Description:
Light to Digital Converters Ambient Light Sensor Light to Digital
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