TSL2563FN Datasheet TSL2562FN, TSL2563T, TSL2563FN | P13-P15

TSL2562, TSL2563

LOW-VOLTAGE

LIGHT-TO-DIGITAL CONVERTER

TAOS066N − AUGUST 2010

The LUMENOLOGY r Company

www.taosinc.com

Data Byte 1Slave AddressS

A A

811 1

Command Code

Data Byte N A

811

Byte Count = N A A

...

811

Data Byte 2 A

...

Figure 16. SMBus Block Write or I

C Write Protocols

NOTE: The I

C write protocol does not use the Byte Count packet, and the Master will continue sending Data Bytes until the Master initiates a

Stop condition. See the Command Register on page 13 for additional information regarding the Block Read/Write protocol.

Byte Count = NSlave AddressS

A A

811 1

Command Code

PData Byte N A

811

Slave Address A A

...

811

Data Byte 2 A

...

Data Byte 1 A

Figure 17. SMBus Block Read or I

C Read (Combined Format) Protocols

NOTE: The I

C read protocol does not use the Byte Count packet, and the Master will continue receiving Data Bytes until the Master initiates

a Stop Condition. See the Command Register on page 13 for additional information regarding the Block Read/Write protocol.

The TSL256x is controlled and monitored by sixteen registers (three are reserved) and a command register

accessed through the serial interface. These registers provide for a variety of control functions and can be read

to determine results of the ADC conversions. The register set is summarized in Table 2.

Table 2. Register Address

ADDRESS RESISTER NAME REGISTER FUNCTION

−− COMMAND Specifies register address

0h CONTROL Control of basic functions

1h TIMING Integration time/gain control

2h THRESHLOWLOW Low byte of low interrupt threshold

3h THRESHLOWHIGH High byte of low interrupt threshold

4h THRESHHIGHLOW Low byte of high interrupt threshold

5h THRESHHIGHHIGH High byte of high interrupt threshold

6h INTERRUPT Interrupt control

7h −− Reserved

8h CRC Factory test — not a user register

9h −− Reserved

Ah ID Part number/ Rev ID

Bh −− Reserved

Ch DATA0LOW Low byte of ADC channel 0

Dh DATA0HIGH High byte of ADC channel 0

Eh DATA1LOW Low byte of ADC channel 1

Fh DATA1HIGH High byte of ADC channel 1

The mechanics of accessing a specific register depends on the specific SMB protocol used. Refer to the section

on SMBus protocols. In general, the COMMAND register is written first to specify the specific control/status

TSL2562, TSL2563

LOW-VOLTAGE

LIGHT-TO-DIGITAL CONVERTER

TAOS066N − AUGUST 2010

The LUMENOLOGY r Company

www.taosinc.com

Command Register

The command register specifies the address of the target register for subsequent read and write operations.

The Send Byte protocol is used to configure the COMMAND register. The command register contains eight bits

as described in Table 3. The command register defaults to 00h at power on.

Table 3. Command Register

6754

ADDRESS

2310

0000 0000Reset Value:

COMMAND

CLEARCMD WORD BLOCK

FIELD BIT DESCRIPTION

CMD 7 Select command register. Must write as 1.

CLEAR 6 Interrupt clear. Clears any pending interrupt. This bit is a write-one-to-clear bit. It is self clearing.

WORD 5

SMB Write/Read Word Protocol. 1 indicates that this SMB transaction is using either the SMB Write Word or

Read Word protocol.

BLOCK 4

Block Write/Read Protocol. 1 indicates that this transaction is using either the Block Write or the Block Read

protocol. See Note below.

ADDRESS 3:0

commands according to Table 2.

NOTE: An I

C block transaction will continue until the Master sends a stop condition. See Figure 16 and Figure 17. Unlike the I2C protocol, the

SMBus read/write protocol requires a Byte Count. All four ADC Channel Data Registers (Ch through Fh) can be read simultaneously in

a single SMBus transaction. This is the only 32-bit data block supported by the TSL2562 SMBus protocol. The BLOCK bit must be set

to 1, and a read condition should be initiated with a COMMAND CODE of 9Bh. By using a COMMAND CODE of 9Bh during an SMBus

Block Read Protocol, the TSL2562 device will automatically insert the appropriate Byte Count (Byte Count = 4) as illustrated in Figure 17.

A write condition should not be used in conjunction with the Bh register.

Control Register (0h)

The CONTROL register contains two bits and is primarily used to power the TSL256x device up and down as

shown in Table 4.

Table 4. Control Register

6754

POWER

2310

0000 0000Reset Value:

CONTROL

ResvResv ResvResv Resv Resv

FIELD BIT DESCRIPTION

Resv 7:2 Reserved. Write as 0.

POWER 1:0

Power up/power down. By writing a 03h to this register, the device is powered up. By writing a 00h to this

NOTE: If a value of 03h is written, the value returned during a read cycle will be 03h. This feature can be

used to verify that the device is communicating properly.

TSL2562, TSL2563

LOW-VOLTAGE

LIGHT-TO-DIGITAL CONVERTER

TAOS066N − AUGUST 2010

The LUMENOLOGY r Company

www.taosinc.com

Timing Register (1h)

The TIMING register controls both the integration time and the gain of the ADC channels. A common set of

control bits is provided that controls both ADC channels. The TIMING register defaults to 02h at power on.

Table 5. Timing Register

6754

INTEG

2310

0000 0010Reset Value:

TIMING

ManualResvResv GAIN ResvResv1h

FIELD BIT DESCRIPTION

Resv 7−5 Reserved. Write as 0.

GAIN 4

Switches gain between low gain and high gain modes. Writing a 0 selects low gain (1×); writing a 1 selects

high gain (16×).

Manual 3

Manual timing control. Writing a 1 begins an integration cycle. Writing a 0 stops an integration cycle.

NOTE: This field only has meaning when INTEG = 11. It is ignored at all other times.

Resv 2 Reserved. Write as 0.

INTEG 1:0 Integrate time. This field selects the integration time for each conversion.

Integration time is dependent on the INTEG FIELD VALUE and the internal clock frequency. Nominal integration

times and respective scaling between integration times scale proportionally as shown in Table 6. See Note 5

and Note 6 on page 5 for detailed information regarding how the scale values were obtained; see page 22 for

further information on how to calculate lux.

Table 6. Integration Time

INTEG FIELD VALUE SCALE NOMINAL INTEGRATION TIME

00 0.034 13.7 ms

01 0.252 101 ms

10 1 402 ms

11 −− N/A

The manual timing control feature is used to manually start and stop the integration time period. If a particular

integration time period is required that is not listed in Table 6, then this feature can be used. For example, the

manual timing control can be used to synchronize the TSL256x device with an external light source (e.g. LED).

A start command to begin integration can be initiated by writing a 1 to this bit field. Correspondingly, the

integration can be stopped by simply writing a 0 to the same bit field.

Interrupt Threshold Register (2h − 5h)

The interrupt threshold registers store the values to be used as the high and low trigger points for the comparison

function for interrupt generation. If the value generated by channel 0 crosses below or is equal to the low

threshold specified, an interrupt is asserted on the interrupt pin. If the value generated by channel 0 crosses

above the high threshold specified, an interrupt is asserted on the interrupt pin. Registers THRESHLOWLOW

and THRESHLOWHIGH provide the low byte and high byte, respectively, of the lower interrupt threshold.

Registers THRESHHIGHLOW and THRESHHIGHHIGH provide the low and high bytes, respectively, of the

upper interrupt threshold. The high and low bytes from each set of registers are combined to form a 16-bit

threshold value. The interrupt threshold registers default to 00h on power up.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42

TSL2563FN

Mfr. #:

Buy TSL2563FN

Manufacturer:

ams

Description:

Light to Digital Converters Ambient Light Sensor Light to Digital

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

TSL2563FN

TSL2563FN

Products related to this Datasheet