September 1993 2
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT652
FEATURES
• Multiplexed real-time and stored
data
• Independent register for A and B
buses
• Independent enables for A and B
buses
• 3-state
• Output capability: Bus driver
• Low power consumption by CMOS
technology
• I
CC
category: MSI.
APPLICATIONS
• Bus interfaces.
DESCRIPTION
The 74HC/HCT652 are high-speed
SI-gate CMOS devices and are pin
compatible with Low power Schottky
TTL (LSTTL). They are specified in
compliance with Jedec standard
no. 7A.
The 74HC/HCT652 consist of 8
non-inverting bus transceiver circuits
with 3-state outputs, D-type flip-flops
and central circuitry arranged for
multiplexed transmission of data
directly from the data bus or from the
internal storage registers. Data on the
“A” or “B” or both buses, will be stored
in the internal registers, at the
appropriate clock pins (CP
AB
or
CP
BA
) regardless of the select pins
(S
AB
and S
BA
) or output enable (OE
AB
and OE
BA
) control pins. Depending
on the select inputs S
AB
and S
BA
data
can directly go from input to output
(real time mode) or data can be
controlled by the clock (storage
mode), this is when the output enable
pins this operating mode permits. The
output enable pins OE
AB
and OE
BA
determine the operation mode of the
transceiver. When OE
AB
is LOW, no
data transmission from A
n
to B
n
is
possible and when OE
BA
is HIGH,
there is no data transmission from B
n
to A
n
possible. When S
AB
and S
BA
are
in the real time transfer mode, it is
also possible to store data without
using the internal D-type flip-flops by
simultaneously enabling OE
AB
and
OE
BA
. In this configuration each
output reinforces its input. Thus when
all other data sources to the two sets
of bus lines are at high-impedance,
each set of the bus lines will remain at
its last state. This type differs from the
HC/HCT646 in one extra
bus-management function. This is the
possibility to transfer stored “A data to
the “B” bus and transfer stored ”B”
data to the ”A” bus at the same time.
The examples at the application
information demonstrate all bus
management functions.
Schmitt-trigger action in the clock
inputs makes the circuit highly
tolerant to slower clock rise and fall
times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; t
r
=t
f
= 6 ns; V
CC
= 4.5 V; C
L
= 50 pF.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW):
P
D
=C
PD
× V
CC
2
× f
i
+ ∑ (C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
∑ (C
L
× V
CC
2
× f
o
) = sum of the outputs
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
− 1.5 V
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PLH
/t
PZL
propagation delay A
n
/B
n
to B
n
/A
n
C
L
= 15 pF;
V
CC
=5 V
13 13 ns
propagation delay CP
AB
/CP
BA
to B
n
/A
n
18 20 ns
propagation delay S
AB
/S
BA
to B
n
/A
n
20 23 ns
t
PHZ
/t
PZL
3-state output enable time OE
AB
/OE
BA
to B
n
/A
n
14 15 ns
t
PHZ
/t
PLZ
3-state output disable time OE
AB
/OE
BA
to B
n
/A
n
12 13 ns
f
max
maximum clock frequency 92 92 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per channel notes 1 and 2 26 28 pF
