74HC652PW,118

September 1993 4
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT652
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
= LOW-to-HIGH transition
2. The data output functions may be enabled or disabled by various signals at OE
AB
and OE
BA
inputs. Data input
functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock
inputs.
INPUTS
(1)
DATA I/O
(2)
OPERATION OR FUNCTION
OE
AB
OE
BA
CP
AB
CP
BA
S
AB
S
BA
A
1
THRU A
8
B
1
THRU B
8
HC/HCT652
L H H or L H or L X X
Input Input
Isolation
LH↑↑X X Store A and B data
XHH or L X X Input Not specified Store A, Hold B
HH↑↑L X Input Output Store A in both registers
L X H or L X X Not specified Input Hold A, Store B
LL↑↑X L Ouput Input Store B in both registers
LLXXXL
Ouput Input
Real Time B Data to A Bus
L L X H or L X H Stored B Data to A Bus
HHXXLX
Input Output
Real Time A Data to B Bus
H H H or L X H X Stored A Data to B Bus
H L H or L H or L H H Output Output
Stored A Data to B Bus and
Stored B Data to A Bus
Fig.4 Functional diagram.
September 1993 5
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT652
Fig.5 Logic diagram.
September 1993 6
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT652
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
I
CC
category: MSI.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
=t
f
= 6 ns; C
L
= 50 pF.
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS+25 40 to +85 40 to +125
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
t
PHL
/t
PLH
propagation delay
A
n
, B
n
to B
n
, A
n
44
16
13
135
27
23
170
34
29
205
41
35
ns 2.0
4.5
6.0
Fig.6
t
PHL
/t
PLH
propagation delay
CP
AB
, CP
BA
to B
n
, A
n
61
22
18
190
38
32
240
48
41
285
57
48
ns 2.0
4.5
6.0
Fig.7
t
PHL
/t
PLH
propagation delay
S
AB
, S
BA
to B
n
, A
n
63
23
18
195
39
33
245
49
42
295
59
50
ns 2.0
4.5
6.0
Fig.8
t
PZH
/t
PZL
3-state output enable
time
OE
AB
, OE
BA
to A
n
, B
n
47
17
14
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.9
t
PHZ
/t
PLZ
3-state output disable
time
OE
AB
, OE
BA
to A
n
, B
n
41
15
12
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.9
t
THL
/t
TLH
output transition time
14
5
4
60
12
10
75
15
13
90
18
15
ns 2.0
4.5
6.0
Figs 6, 8
t
W
clock pulse width
HIGH or LOW
CP
AB
or CP
BA
80
16
14
17
6
5
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.7
t
su
set-up time
A
n
, B
n
to CP
AB
, CP
BA
100
20
17
17
6
5
125
25
21
150
30
26
ns 2.0
4.5
6.0
Fig.7
t
h
hold time
A
n
, B
n
to CP
AB
, CP
BA
25
5
4
8
3
2
30
6
5
35
7
6
ns 2.0
4.5
6.0
Fig.7
f
max
maximum clock pulse
frequency
6.0
30
35
16
83
98
4.8
24
28
4.0
20
24
MHz 2.0
4.5
6.0
Fig.7

74HC652PW,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC TXRX NON-INVERT 6V 24TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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