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A8587KEJTR-T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
A8587
13
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
(9)
L
O
× ESL
+
ΔV
OUT
= ΔI
L
× ESR +
ΔI
L
V
IN
–
V
OUT
8×f
SW
×C
OUT
where L
O
is the inductor value, ESR is the equivalent series
resistance of the output capacitor, and ESL is its equivalent series
inductance.
The type of output capacitors will determine which terms of
equation 9 are dominant. For ceramic output capacitors, the ESR
and ESL are virtually zero, so the output voltage ripple will be
dominated by the third term of equation 10:
(10)
ΔV
OUT
=
ΔI
L
8 × f
SW
× C
OUT
To reduce the voltage ripple of a design using ceramic output
capacitors, simply increase the total capacitance, reduce the
inductor current ripple (that is, increase the inductor value), or
increase the switching frequency.
For electrolytic output capacitors, the value of capacitance will be
relatively high, so the third term in equation 9 will be very small.
The output voltage ripple will be determined primarily by the
first two terms of equation 9:
(11)
L
O
× ESLΔV
OUT
= ΔI
L
× ESR +
V
IN
–
V
OUT
To reduce the voltage ripple of a design using electrolytic output
capacitors, simply decrease the equivalent ESR and ESL by using
a higher-quality capacitor, add more capacitors in parallel, or
reduce the inductor current ripple (that is increase the inductor
value).
The ESR of some electrolytic capacitors can be quite high, so
Allegro recommends choosing a quality capacitor that clearly
documents the ESR, or the total impedance, in the datasheet.
Also, the ESR of electrolytic capacitors usually increases sig-
nificantly at cold temperatures—by as much as 10×— which
increases the output voltage ripple and in most cases significantly
reduces the stability of the system.
The transient response of the regulator depends on the number
and type of output capacitors. In general, minimizing the ESR of
the output capacitance will result in a better transient response.
The ESR can be minimized by simply adding more capacitors in
parallel or by using higher-quality capacitors. At the instant of a
fast load transient (di/dt), the output voltage will change by the
amount:
(12)
dt
× ESLΔV
OUT
= ΔI
OUT
× ESR +
di
After the load transient occurs, the output voltage will deviate
from its nominal value for a short time. This time will depend
on the system bandwidth, the output inductor value, and output
capacitance. Eventually, the error amplifier will bring the output
voltage back to its nominal value.
The speed at which the error amplifier will bring the output volt-
age back to its set point will depend mainly on the closed-loop
bandwidth of the system. A higher bandwidth usually results in
a shorter time to return to the nominal voltage. However, accept-
able gain and phase margins may be more difficult to obtain with
a higher-bandwidth system. Selection of the compensation com-
ponents (R
Z
, C
Z
, C
P
) are discussed in more detail in the Compen-
sation Components section of this datasheet.
Low-I
Q
PFM Output Voltage Ripple Calculation
After choosing an output inductor and an output capacitor or
capacitors, it is important to calculate the output voltage ripple
(ΔV
OUT(PFM)
) during Low-I
Q
PFM mode. With ceramic output
capacitors, the output voltage ripple in PWM mode is usually
negligible, but that is not the case during Low-I
Q
PFM mode.
The PFM-mode comparator requires about 10 mV or greater of
voltage ripple on the VOUT pin and generates groups of pulses
to meet this requirement. However, if a single pulse results in a
voltage ripple greater than 10 mV, then the voltage ripple would
be dictated by that single pulse. To calculate the voltage ripple
from that single pulse, first the peak inductor current must be
calculated with slope compensation taken into account. The
I
PEAK(LO_IQ)
specification does not include slope compensation;
therefore, the peak inductor current operating point is calculated
as follows:
(13)
I=
PEAK_L
I
PEAK(LO_IQ)
V
IN
– V
OUT
S× L
EO
1 +
Then, calculate the MOSFET on-time (t
ON(Q)
) and freewheeling
diode on-time (t
ON(D)
) (Figure 3). The on-time is defined as the
time it takes for the inductor current to reach I
PEAK_L
:
(14)
t=
ON(Q)
I× L
PEAK_L O
V–V–I× (R + L)
IN OUT PEAK_L DS(on)HSO(DCR)
where R
DS(on)
is the on-resistance of the internal high-side MOS-
FET (150 mΩ typical) and L
O(DCR)
is the DC resistance of the
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
A8587
14
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
output inductor (L
O
). During this rising time interval, the length
of time for the inductor current to rise from 0 A to I
OUT
is:
(15)
t=
1
I× L
OUT O
V–V–I× (R + L)
IN OUT PEAK_L DS(on)HSO(DCR)
The freewheeling diode on-time is defined as the time it takes for
the inductor current to decay from I
PEAK_L
to 0 A:
t=
ON(D)
I× L
PEAK_L O
V+ V
OUT F
(16)
During this falling time interval, the length of time for the induc-
tor current to fall from I
OUT
to 0 A is:
t=
2
I× L
OUT O
V+ V
OUT F
(17)
t
I
PEAK(LO_IQ)
I
OUT
t
V
PP(LO_IQ)
t
2
t
1
t
ON(Q)
t
ON(D)
I
L
V
OUT
Figure 4: Calculating the Output Ripple Voltage in
PFM Mode
Given the peak inductor current (I
PEAK_L
) and the rise and fall
times (t
ON(Q)
and t
ON(D)
) for the inductor current, the output volt-
age ripple can be calculated for a signal pulse as follows:
(18)
V=
PP(LO_IQ)
I–I
PEAK_L OUT
2 × C
OUT
(t + t–t–t
ON(Q) ON(D)21
)
×
If V
PP(LO_IQ)
is greater than the ~10 mV ripple that the PFM
comparator requires, then the output capacitance or inductor can
be adjusted to reduce the PFM-mode voltage ripple. In PFM
mode, decreasing the inductor value reduces the PFM ripple, but
may negatively impact the PWM voltage ripple, maximum load
current in PWM mode, or change the mode of operation from
CCM to DCM.
If V
PP(LO_IQ)
is less than the ~10 mV requirement, the A8587
operates with multiple pulses at the PWM frequency to meet the
ripple requirement. The fixed-frequency operation may result in
DCM or CCM operation during the multiple pulses.
Compensation Components
A8587 employs current-mode control for easy compensation
and fast transient response. The system stability and transient
response are controlled through the COMP pin. COMP pin is the
output of the internal transconductance error amplifier. A series
capacitor-resistor combination sets a pole-zero pair to control the
characteristics of the control system. The DC voltage gain, A
VDC
,
of the feedback loop is given by:
(19)
A
=
VDC
V
FB
I
OUT
× G×A×
CS VOL
V
OUT
V
OUT
where A
VOL
is the error amplifier voltage gain, 1000 V/V. G
CS
is
the current-sense transconductance, 9 A/V.
The system has two noteworthy poles: one is due to the compen-
sation capacitor (C
Z
) and the error amplifier output resistor; the
other is due to the output capacitor and the load resistor. These
poles are located at:
(20)
f=
P1
g
m
2π × C×A
ZVOL
(21)
f=
P2
I
OUT
2π × C× V
OUT
OUT
where g
m
is the error amplifier transconductance, 60 μA/V.
The system has one noteworthy zero. This is due to the compen-
sation capacitor (C
Z
) and the compensation resistor (R
Z
). This
zero is located at:
(22)
f=
Z
1
2π × C× R
ZZ
The system may have another zero, if the output capacitor has a
large capacitance, or a high ESR value, or both. The zero, due to
the ESR and capacitance of the output capacitor, is located at:
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
A8587
15
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
(23)
f=
Z
1
2π × C× ESR
OUT
In this case (as shown in the simplified schematic on page 1), a
third pole set by the optional compensation capacitor (C
P
) and the
compensation resistor (R
Z
) is used to compensate the effect of the
ESR zero on the loop gain. This pole is located at:
(24)
f=
P3
1
2π × C× R
PZ
The goal of compensation design is to shape the converter
transfer function to get a desired loop gain. The system crossover
frequency where the feedback loop has unity gain is impor-
tant. Lower crossover frequencies result in slower line and load
transient responses, while higher crossover frequencies could
cause the system to be unstable. A good rule of thumb is to set the
crossover frequency to approximately one tenth of the switching
frequency. Table 3 lists typical values of compensation com-
ponents for some standard output voltages with various output
ceramic capacitors and inductors. The values of the compensation
components have been optimized for fast transient responses and
good stability.
Table 3: Compensation Values for Typical Output Voltage/
Capacitor Combinations with f
SW
= 500 kHz
V
OUT
(V)
L
O
(µH)
C
OUT
(µF)
R
Z
(kΩ)
C
Z
(pF)
C
P
1.8 4.7 47 105 100 None
2.5 4.7 to 6.8 22 54.9 220 None
3.3 6.8 to 10 22 68.1 220 None
5 15 to 22 22 100 150 None
12 22 to 33 22 147 150 None
To optimize the compensation components for conditions not
listed in Table 3, the following procedure can be used:
1. Choose the compensation resistor (R
Z
) to set the desired
crossover frequency (f
C
). Determine the R
Z
value by the fol-
lowing equation:
(25)
R
=
Z
g× G
mCS
V
FB
2π × C× f
OUT C
V
×
OUT
2. Choose the compensation capacitor (C
Z
) to achieve the
desired phase margin. For applications with typical inductor
values, setting the compensation zero (f
Z1
) below one fourth
of the crossover frequency provides sufcient phase margin.
Determine the C
Z
value by the following equation:
(26
)
C>
Z
4
2π × R× f
ZC
3. Determine if the second compensation capacitor (C
P
) is
required. It is required if the ESR zero of the output capacitor
is located at less than half of the switching frequency or the
following relationship is valid:
(27)
<
1 f
SW
2π × C× ESR
OUT
2
If this is the case, then add the second compensation capaci-
tor (C
P
) to set the pole f
P3
at the location of the ESR zero.
Determine the C
P
value by the equation:
(28)
C=
P
R
Z
C× ESR
OUT
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

A8587KEJTR-T

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IC REG BUCK ADJUSTABLE 2A 10DFN
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