Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
A8587
7
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
FUNCTIONAL DESCRIPTION
Overview
The A8587 is a PWM buck regulator that incorporates all of the
control and protection circuitry necessary to satisfy a wide range
of low-voltage applications. The A8587 employs current-mode
control to provide fast transient response, simple compensation,
and excellent stability.
The features of the A8587 include a ±3% reference, an adjust-
able switching frequency, a transconductance error amplifier, an
enable input, integrated power MOSFET, fixed soft-start time,
and low-current sleep mode.
The protection features of the A8587 include undervoltage
lockout (UVLO), cycle-by-cycle overcurrent protection (OCP),
hiccup-mode short-circuit protection (HIC), overvoltage protec-
tion (OVP), and thermal shutdown (TSD).
PWM Control
The A8587 includes a high-speed PWM comparator, capable of
pulse widths less than 100 ns. The inverting input of the com-
parator is connected to the output of the error amplifier. The non-
inverting input is connected to the current-sense signal.
At the beginning of each PWM cycle, the PWM_CLK signal
sets the PWM flip-flop and the high-side MOSFET is turned
on. When the current-sense signal rises above the error ampli-
fier voltage, the comparator resets the PWM flip-flop and the
high-side MOSFET is turned off. It remains off for at least 100 ns
before the next cycle can be initiated.
Low-I
Q
Pulse-Frequency-Modulation (PFM)
Mode
At light loads, the PFM comparator, which is connected to the
FB pin, modulates the frequency of the SW node to regulate the
output voltage with very high efficiency.
The reference for the PFM comparator is calibrated approxi-
mately 1% above the PWM regulation point. When the voltage at
the internal FB point rises above the PFM comparator threshold
and peak inductor current falls below I
PEAK(LO_IQ)
(800 mA)
minus slope compensation, the device will enter PFM-coast
mode, tri-stating the SW node and drawing extremely low cur-
rent from VIN. When voltage at the FB point falls below the
PFM comparator threshold, the device will fully power-up after
approximately a 2.5 μs delay, and the high-side MOSFET is
repeatedly turned on, operating at the PWM switching frequency,
until the voltage at the FB pin rises above the PFM comparator
threshold. V
OUT
will rise at a rate determined by—and have a
voltage ripple dependent on—the input voltage, output voltage,
inductor value, output capacitance, and load. In addition, the
transition point from PWM to PFM mode is defined by the input
voltage, output voltage, slope compensation, and inductor value.
Error Amplifier
The primary function of the transconductance error amplifier is
to regulate the A8587 output voltage. The error amplifier appears
as a device with three inputs: two positive and one negative. The
negative input is simply connected to the FB pin and is used to
sense the feedback voltage for regulation. The two positive inputs
are connected to the internal soft-start and reference voltages. The
error amplifier performs an analog OR selection between them;
it regulates to either the soft-start voltage or the A8587 internal
reference (V
REF
), whichever is lower.
To stabilize the regulator, a series RC compensation network
(R
Z
C
Z
) must be connected from the error amplifier output
(COMP pin) to GND, as shown in the typical application sche-
matic. In most applications, an additional low-value capacitor
(C
P
) should be connected in parallel with the R
Z
C
Z
compen-
sation network to roll-off the loop gain at higher frequencies.
However, if the C
P
capacitor is too large, the phase margin of the
regulator may be reduced.
During operation, the minimum COMP voltage is clamped to
750 mV, and its maximum is clamped to 1.5 V. COMP is inter-
nally pulled down to GND during fault conditions.
Slope Compensation
The A8587 incorporates internal slope compensation (S
E
) to
allow PWM duty cycles above 50% for a wide range of input and
output voltages and inductor values. The slope compensation sig-
nal is added to the sum of the current-sense amplifier output and
the PWM ramp offset. The amount of slope compensation scales
with the maximum on-time (1/f
SW
– t
OFF(MIN)
), centered around
3.1 A/μs at 2 MHz. The value of the output inductor should be
chosen such that S
E
is between 0.5× and 1× the falling slope of
the inductor current (S
F
).
Internal Regulator
An internal series pass regulator (LDO) generates around 2.9 V
for most of the internal circuits of the A8587. The power for this
LDO is derived from VIN. The LDO is in full regulation once
V
IN
is greater than 3 V.
