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A8587KEJTR-T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
A8587
4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Terminal List Table
Pin
Name
Pin
Number
Description
SW 1
The source of the internal MOSFET. The output inductor (L
O
) and cathode of the freewheel diode (D) should be connected to
this pin. L
O
and D should be placed as close as possible to this pin and connected with relatively wide traces.
EN 2
Enable input. This pin is a high-voltage input that turns the regulator on or off. Set this pin high to turn the regulator on or set
this pin low to turn the regulator off.
COMP 3
Output of the error amplifier and compensation node for the current-mode control loop. Connect a series RC network from this
pin to GND for loop compensation. See the Applications section of this datasheet for further details
FB 4
Feedback (negative) input to the error amplifier. Connect a resistor divider from the regulator output node, VOUT, to this pin to
program the output voltage.
NPOR 5
Active-low power-on reset output signal. This pin is an open-drain output that transitions from low-impedance to high-impedance
when the output is within the final regulation voltage.
GND 6 Ground connection.
FREQ 7
Frequency setting pin. A resistor, R
FREQ
, from this pin to GND sets the PWM switching frequency. See Table 1 and Figure 2 to
determine the value of R
FREQ
.
VIN 8,9
Power input for the control circuits and the drain of the internal high-side N-channel MOSFET. Connect this pin to a power
supply of 3.8 to 36 V. A high-quality ceramic capacitor should be placed very close to this pin and GND.
BST 10
Bootstrap capacitor connection. Connect a 100 nF capacitor from this pin to the SW pin. The voltage on this capacitor drives
the internal MOSFET via the high-side gate driver. A series BOOT resistor is not recommended.
SW
EN
COMP
FB
NPOR
BST
VIN
VIN
FREQ
GND
PAD
1
2
3
4
5
6
7
8
9
10
Package EJ Pinouts
PINOUT DIAGRAM AND TERMINAL LIST TABLE
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
A8587
5
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
GENERAL SPECIFICATIONS
Operating Input Voltage V
IN
V
EN
≥ 2.5 V 3.8 12 36 V
V
IN
UVLO Start V
IN(START)
V
IN
rising 2.6 3 3.4 V
V
IN
UVLO Hysteresis V
IN(HYS)
– 0.4 – V
Supply Quiescent Current
[1]
I
Q
No load, V
FB
= 0.9 V – 27 36 µA
I
Q(SLEEP)
V
EN
= 0 V – 11 18 µA
PWM SWITCHING FREQUENCY
Switching Frequency f
SW
R
FSET
= 45 kΩ 1.6 2.0 2.4 MHz
THERMAL PROTECTION
Thermal Shutdown Threshold
[2]
T
TSD
T
J
rising – 170 – °C
Thermal Shutdown Hysteresis
[2]
T
HYS
– 20 – °C
PULSE-WIDTH MODULATION (PWM)
Minimum On-Time
[2]
t
ON(MIN)
– 80 160 ns
Minimum Off-Time
[2]
t
OFF(MIN)
– 100 – ns
INTERNAL MOSFET
MOSFET On-Resistance R
DS(on)
V
BOOT-SW
= 5 V – 150 – mΩ
MOSFET Leakage I
FET(LKG)
V
EN
= 0 V, V
IN
= 12 V, V
SW
= 0 V, T
J
= 25°C – 0.1 1 µA
ERROR AMPLIFIER
Feedback Voltage V
FB
4.5 V ≤ V
IN
≤ 36 V, T
J
= 25°C 0.786 0.792 0.803 V
4.5 V ≤ V
IN
≤ 36 V, –40°C ≤ T
J
≤ 125°C 0.773 0.812 V
Error Amp Voltage Gain
[2]
A
VOL
– 1000 – V/V
Error Amp Transconductance
[2]
g
m
I
COMP
= ±3 µA 35 60 95 µA/V
Error Amp Min Source Current I
EA(SOURCE)
V
FB
= 0.7 V – –5 – µA
Error Amp Min Sink Current I
EA(SINK)
V
FB
= 0.9 V – 5 – µA
Low I
Q
Peak Current Threshold I
PEAK(LO_IQ)
– 350 – mA
SOFT-START
Soft-Start Ramp Time
[2]
t
SS
0 V < V
FB
< 0.8 V – 1.5 – ms
CURRENT PROTECTION
Current Limit I
LIM
2.3 2.7 – A
COMP to Current-Sense
Transductance
[2]
G
CS
– 4.5 – A/V
Slope Compensation S
E(2MHz)
Measured at f
SW
= 2 MHz – 1.5 – A/µs
LOGIC ENABLE
EN Threshold Rising V
EN(H)
V
EN
rising 1.2 1.5 1.85 V
EN Threshold Falling V
EN(L)
V
EN
falling 1.0 1.2 1.4 V
EN Hysteresis V
EN(HYS)
– 300 – mV
ELECTRICAL CHARACTERISTICS
[1]
: Valid for V
IN
= 12 V, V
EN
= 2.5 V, V
COMP
= 1.4 V, –40°C ≤ T
J
≤ 125°C, typical values at T
J
= 25°C,
unless otherwise specified
1
For input and output current specications, negative current is dened as coming out of the node or pin (sourcing), positive current is dened as going into the node or pin
(sinking).
2
Ensured by design and characterization, not production tested.
Wide Input Voltage, Adjustable Frequency, 2 Amp
Non-Synchronous Buck Regulator with Enable and NPOR
A8587
6
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
POWER-ON RESET (NPOR)
Undervoltage Threshold (Falling) V
NPOR(UV)
NPOR = low 710 730 750 mV
Undervoltage Hysteresis V
NPOR(HYS)
NPOR = low – 15 – mV
Overvoltage Threshold (Rising) V
NPOR(OV)
NPOR = low 840 880 920 mV
NPOR Rising Delay t
d(NPOR)
5 7.5 10 ms
NPOR Output Voltage V
NPOR
I
NPOR
= 10 mA, fault asserted – – 500 mV
Minimum V
IN
for Correct Operation
of NPOR
V
IN(NPOR)
NPOR pull-up of 2 kΩ to 5 V – 3.5 – V
NPOR Leakage
[2]
I
NPOR
V
NPOR
= 5.5 V, fault not asserted – – 1 μA
1
For input and output current specications, negative current is dened as coming out of the node or pin (sourcing), positive current is dened as going into the node or
pin (sinking).
2
Ensured by design and characterization, not production tested.
ELECTRICAL CHARACTERISTICS
[1]
(continued): Valid for V
IN
= 12 V, V
EN
= 2.5 V, V
COMP
= 1.4 V, –40°C ≤ T
J
≤ 125°C, typical values
at T
J
= 25°C, unless otherwise specified
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

A8587KEJTR-T

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IC REG BUCK ADJUSTABLE 2A 10DFN
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