1
PS8545D 11/12/08
V
DDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
15
16
Y4
FBIN
V
DDQ
GND
Y3
Y3
GND
FBIN
FBOUT
FBOUT
V
DDQ
Y4
GND
Y0
Y0
CLK
CLK
Y1
GND
V
DDQ
V
DDQ
AGND
Y2
Y2
Y1
GND
AV
DD
Description
PI6CV855 PLL clock device is developed for SSTL_DDR SDRAM
applications. This PLL Clock Buffer is designed for 2.5 V
DDQ
and
2.5V AV
DD
operation and differential data input and output levels.
The device is a zero delay buffer that distributes a differential clock
input pair (CLK, CLK) to five differential pairs of clock outputs
(Y[0:4], Y[0:4]) and one differential pair feedback clock outputs
(FBOUT, FBOUT). The clock outputs are controlled by the input
clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), and the
Analog Power input (AV
DD
). When the AV
DD
is strapped low, the
PLL is turned off and bypassed for test purposes.
The PI6CV855 is able to track Spread Spectrum Clocking to reduce
EMI.
Features
• PLL clock distribution optimized for SSTL_2 DDR SDRAM
applications.
• Distributes one differential clock input pair to five differential
clock output pairs.
• Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2
• Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2
• External feedback pins (FBIN,FBIN) are used to
synchronize the outputs to the input clocks.
• Operates at AV
DD
= 2.5V for core circuit and internal PLL,
and V
DDQ
= 2.5V for differential output drivers
• Packaging (Pb-free & Green available):
– 28-pin TSSOP (L)
Block Diagram
PI6CV855
PLL Clock Driver for 2.5V
SSTL
2 DDR SDRAM Memory
28-Pin
L
Pin Configuration
Y0
Y0
Y1
AV
DD
FBIN
FBIN
CLK
CLK
PLL
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Logic
and
Test Ciruit
FBOUT
FBOUT
