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PI6CV855LE

P1-P3P4-P6P7-P9
7
PS8545D 11/12/08
PI6CV855
PLL Clock Driver for 2.5V
SSTL 2 DDR SDRAM Memory
Figure 3. Cycle-to-Cycle Jitter
Figure 4. Static Phase Offset
Figure 5. Output Skew
FBIN
FBIN
CLK
CLK
t
( )
n
t
( )
n+1
t
=
∑
1
n=N
t
( ) n
N
(N is a large number of samples)
t
jit(cc)
=
t
cycle n
-
t
cycle n+1
t
cycle n+1
t
cycle n
Yx,FBOUT
Yx,FBOUT
t
sk(o)
Yx
Yx
Yx, FBOUT
Yx, FBOUT
08-0298
8
PS8545D 11/12/08
PI6CV855
PLL Clock Driver for 2.5V
SSTL 2 DDR SDRAM Memory
Figure 6. Period Jitter
Figure 7. Half-Period Jitter
Figure 8. Input and Output Slew Rates
Clock Inputs
and Outputs
V
DDQ
0V
t
sl(i),
t
sl(o)
80%
20%
t
sl(i),
t
sl(o)
80%
20%
Yx, FBOUT
Yx, FBOUT
Yx, FBOUT
Yx, FBOUT
t
cycle n
f
O
1
t
jit(per)
=
t
cycle n
f
O
1
Yx, FBOUT
Yx, FBOUT
t
half period n
t
n+1
half period
f
O
1
t
jit(hper)
=
t
half period n
2*f
O
1
08-0298
9
PS8545D 11/12/08
PI6CV855
PLL Clock Driver for 2.5V
SSTL 2 DDR SDRAM Memory
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
Packaging Mechanical: 28-Pin TSSOP (L)
1
DESCRIPTION: 28-Pin, 173-Mil Wide, TSSOP
PACKAGE CODE: L
DOCUMENT CONTROL NO.
PD - 1313
REVISION: D
DATE: 03/09/05
Pericom Semiconductor Corporation
3545 N. 1st Street, San Jose, CA 95134
1-800-435-2335 • www.pericom.com
.378
.386
.047
1.20
.002
.006
SEATING
PLANE
.0256
BSC
.018
.030
.252
BSC
1
28
.169
.177
0.05
0.15
6.4
0.45
0.75
0.09
0.20
4.3
4.5
9.6
9.8
0.65
0.19
0.30
.007
.012
.004
.008
Max
Note:
1. Package Outline Exclusive of Mold Flash and Metal Burr
2. Controlling dimentions in millimeters
3. Ref: JEDEC MO-153F/AE
Ordering Information
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
Ordering Code Package Code Package Type
PI6CV855LE L Pb-free & Green, 28-pin 173-mil wide TSSOP
08-0298
P1-P3P4-P6P7-P9

PI6CV855LE

Mfr. #:
Buy PI6CV855LE
Manufacturer:
Description:
IC PLL CLKDVR SSTL_2 DDR 28TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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