5
PS8545D 11/12/08
PI6CV855
PLL Clock Driver for 2.5V
SSTL 2 DDR SDRAM Memory
AC Specifications
Switching characteristics over recommended operating free-air temperature range, f
CLK
> 100 MHz (unless otherwise noted).
(See Figure 1 and 2)
retemaraPnoitpircseDmargaiD
VA
CC
V,
QDD
V2.0±V5.2=
stinU
.niM.moNxaM
(t θ)tesffoesahpcitatS
)1(
4erugiF05–005
sp
)cc(tijtrettijelcyc-ot-elcyC3erugiF57–57
)rep(tijtrettijdoireP6erugiF57–57
)reph(tijtrettijdoirep-flaH7erugiF001–001
)i(lstetarwelskcolctupnI
)2(
8erugiF0.10.2
sn/V
)o(lstetarwelskcolctuptuO
)2(
8erugiF0.10.2
)o(kstwekskcolctuptuO5erugiF001sp
sretemarapgniwollofehthtiwsrezisehtnysCSSgnitroppuselihwsretemarapevobaehtllasteem558VC6IPehtnoLLPehT
)3(
.
ycneuqerfnoitaludomCSS0.030.05zHk
noitaivedycneuqerftupnikcolcCSS00.005.0–%
htdiwdnabpoolLLP2zHM
elgnaesahP 130.0–seerged
Notes:
1. Static Phase offset does not include jitter.
2. The slew rate is determined from the IBIS model with test load shown in Figure 1.
3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
