NCP81174
www.onsemi.com
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DETAILED DESCRIPTION
General
The NCP81174, a 4/3/2−phase synchronous buck
controller with PWM VID interface in a QFN−32 package,
provides a compact−footprint power management solution
for new generation computing and graphic processors. It
receives power saving input (PSI) from processors and
operates in 1−phase forced PWM or diode emulation mode
to obtain high efficiency in light−load conditions. It can
either receive PWMVID from the processor to achieve
dynamic voltage control or locally set the reference from an
internal precise 2 V regulator. Operating in high switching
frequency up to 1 MHz allows employing small size
inductor and capacitors. Introduction of dual−edge current
mode multi−phase control results in fast transient response
and good dynamic current balance.
Power Operation Modes
The NCP81174 has three power operation modes
corresponding to PSI levels as shown in Table 1 and 2. The
chip is compatible to different I/O systems. If the upstream
controller has a 3.3 V or higher I/O interface, the
configuration would follow Table 1, the ENABLE signal
needs to be higher than 2.5 V to turn on the chip; If the
upstream controller has a 1.8 V I/O interface, the
configuration would follow Table 2, the ENABLE signal
needs to be higher than 1.1 V only to turn on the chip. The
operation mode can be changed on the fly.
Table 1. POWER SAVING INTERFACE (PSI) CONFIGURATIONS (3.3 V I/O, EN > 2.5 V)
PSI Level Power Mode Phase Configuration
High (PSI ≥ 2.4 V) PS0 Full Phase, FCCM
Intermediate (0.8V < PSI < 2.4 V) PS1 1−Phase, FCCM
Low (PSI ≤ 0.8 V) PS2 1−Phase, Auto CCM/DCM
Table 2. POWER SAVING INTERFACE (PSI) CONFIGURATIONS (1.8 V I/O, 2.5 V > EN > 1.1 V)
PSI Level Power Mode Phase Configuration
High (PSI ≥ 1.4 V) PS0 Full Phase, FCCM
Intermediate (0.8 V < PSI < 1.4 V) PS1 1−Phase, FCCM
Low (PSI ≤ 0.8 V) PS2 1−Phase, Auto CCM/DCM
Remote Voltage Sense
A true differential amplifier allows the NCP81174 to
measure Vcore voltage feedback with respect to the Vcore
ground reference point by connecting the Vcore reference
point to VSP, and the Vcore ground reference point to VSN.
This configuration keeps ground potential differences
between the local controller ground and the Vcore ground
reference point from affecting regulation of Vcore between
Vcore and Vcore ground reference points. The remote
sensing amplifier also subtracts the REFIN (DAC) voltage,
thereby producing an unamplified output error voltage at the
DIFFOUT pin. This output also has a 1.3 V bias voltage as
the floating ground to allow both positive and negative error
voltages.
VSN
VSP
DIFFOUT
REFIN
Figure 4. Voltage Remote Sense
